HPEC Demo Highlights >95% Data Transfer Efficiency of SRIO in an OpenVPX System
ASHBURN, VA – March 13, 2012 – Curtiss-Wright Controls Defense Solutions (CWCDS), a business unit of Curtiss-Wright Controls, has announced that it has successfully demonstrated extremely high data transfer efficiency in an OpenVPX-based High Performance Embedded Computing (HPEC) system. The demonstration featured the world’s first HPEC 6U VPX subsystem in which Serial RapidIO® (SRIO) data was transmitted between an Intel® 2nd Generation Core® i7 processor, Freescale® 8640 Power® Architecture processor and a Xilinx® Virtex®-6 FPGA, the three leading building blocks of high performance Digital Signal Processing (DSP) embedded systems for defense and aerospace C4ISR applications such as image, signal and radar processing. The demonstration, based on Curtiss-Wright’s rugged COTS OpenVPX board modules, was also the industry’s first to show an Intel CPU running Gen 2 SRIO, an achievement made possible through use of the IDT’s groundbreaking Tsi721 PCIe2-to-SRIO2 RapidIO bridge. Results of the demonstration include data transfers between Intel CPUs rated at 1.7GB/s achieving 95% of the theoretical maximum wire speed for a given physical link into the switch fabric. Furthermore, these results were achieved with a near zero overhead burden on the processor thanks to the high-speed DMA feature of the Tsi721 and SRIO’s inherent guaranteed-by-hardware data transmission.
With support for both Gen1 and Gen2 SRIO and true interoperability between all three of the embedded industry’s most popular processor and FPGA device types, this demonstration highlights the advances that have been made in bringing open standard-based HPEC processing to rugged military embedded systems.
“Gen2 Serial RapidIO is the highest speed fabric available to date for use in OpenVPX systems, with speeds up to 20 Gbps. Using the Tsi721 in a x4 configuration at 5 Gbaud, resulting performance was 40% faster than 10 Gigabit Ethernet,” said Lynn Bamford, senior vice president and general manager of Curtiss-Wright Controls Defense Solutions. “We are very excited to be the first COTS system solutions provider to demonstrate the levels of interoperability to make high performance HPEC systems practical and cost-effective. The emergence of COTS-based HPEC processing in compact, rugged deployable subsystems promises to deliver supercomputing performance in SWaP-constrained embedded military applications.”
“We are pleased to deliver the Tsi721 into the embedded computing market, allowing customers to cluster large systems with PCIe enabled processors such as the Intel Core i7 with the 20 Gbps per link performance of RapidIO Gen2 based systems,” said Tom Sparkman, vice president and general manager of the Communications Division at IDT. “With our production RapidIO Gen2 switches and PCIe2-to-SRIO2 bridge, customers such as Curtiss-Wright Controls Defense Solutions are able to provide highly scalable, high bandwidth, low latency multi-processor systems while delivering 95% of available bandwidth into i7 processors. This is achieved with 40% higher performance than Ethernet options and with no protocol termination overhead.”
The SRIO Interoperability Demonstration comprised:
Intel 2nd Generation Core i7 CPU to Intel 2nd Generation Core i7 CPU SRIO data transmission using the IDT Tsi721 PCIe to SRIO bridge
Intel 2nd Generation Core i7 CPU to Freescale 8640 SRIO data transmission
Intel 2nd Generation Core i7 CPU to Xilinx Virtex6 (with SRIO endpoint IP) FPGA SRIO data transmission
Use of IDT CPS1432 Gen2 SRIO switch
Use of IDT Tsi578 Gen1 SRIO switch
The Intel processors were located on the Curtis Wright CHAMP-AV8 dual 2nd Generation Core i7 boards.
The 8640 processor and Xilinx Virtex6 FPGA were located on the Curtiss Wright CHAMP-FX3 FPGA processing engine with FMC I/O expansion.
All of the SRIO transfers in the demonstration were bi-directional. Interoperation included successful use of three different DMA engines native to each device: Tsi721, 8640 and Xilinx V6.
Curtiss-Wright Continuum HPEC Subsystem Components
The CHAMP-AV8 and CHAMP-FX3 are examples of elements of Curtiss-Wright’s Continuum HPEC initiative. Continuum HPEC systems consist of a large number of distributed processors, IO, and software stacks connected by a low latency system fabric. HPEC capabilities are developed in our Ashburn, VA, HPEC Center of Excellence. With scalable architectures, dataflow modeling and configuration validation, Curtiss-Wright’s Continuum HPEC customers can source embedded supercomputing platforms that integrate Intel®-based multi-processor boards with AVX, GPGPU co-processors, Xilinx® Virtex® 6 FPGAs, SRIO and Ethernet switching with Open Standard software solutions including VxWorks®, and Linux with OpenMPI and OFED software interfaces. Supported products include Curtiss-Wright’s CHAMP-FX3 Virtex6 FPGA board, the CHAMP-AV8 dual 2nd Generation Core® i7-based multiprocessor board, the VPX6-1956 2nd Generation Core i7 SBC, the VPX6-6902 sRIO/Ethernet switch, and the VPX6-490 GPGPU module. OpenVPX enclosures are supported including a small 5-6 slot and 19″ rack 16-slot air-cooled Chassis.
For price and availability information on CWCDS HPEC solutions, please contact the factory. Visit our website for more information on the CHAMP-AV8 and the CHAMP-FX3.