IIT Madras Open Source Processor Project

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RapidIO.org member, Indian Institute of Technology has announced an exciting new open source processor project called “Shakti”.  Under the leadership of Project Coordinators, Professor. V. Kamakoti (veezhi@gmail.com) and G. S. Madhusudan (mail@gsmadhusudan.net) a team of Research Scholars [Neel Gala (neelgala@gmail.com), Bodduna Rahul (rahul.bodduna@gmail.com) and Arjun Menon (c.arjunmenon@gmail.com)] at the Indian Institute of Technology – Madras Computer Architecture and Systems Lab  (IIT-Madras CASL) are developing an open source processor architecture called Shakti.  As defined in wikipedia.org, “Shakti (Sanskrit pronunciation: [ˈʃʌktɪ]) (Devanagari: शक्ति; from Sanskrit shak, “to be able”), meaning “power” or “empowerment,” is the primordial cosmic energy and represents the dynamic forces that are thought to move through the entire universe in Hinduism”.

The SHAKTI processor project aims to build 6 processor variants (see below) based on the RISC-V ISA from UC Berkeley (www.riscv.org). The project will develop a complete reference SoC for each family which will serve as an exemplar for that category of processor. While the cores and most of the SoC components (including bus and interconnect fabrics) will be in open source, some standard components such as a PCIe controller, DDR controller and PHY IP will be proprietary 3rd party IP and will not be available under an open source license.

All IIT-Madras CASL source code for this project will be licensed using a 3 part BSD license and will be royalty and patent free (IIT-Madras will not assert any patents). While the primary focus is research, the SoCs are being designed to be competitive with commercial processors with respect to features, silicon area, power profile and frequency. This of course assumes that an optimal layout process is used to tape out the IIT-Madras SHAKTI designs. All of the processor variants will be built and validated using Xilinx FPGAs. The Xilinx based designs will also be made available.

The IIT-Madras CASL team plans to tape out a few of the processor variants, but given the foundry NDA requirements, layout/backend data will not be published.

SHAKTI Processor Variants

C class microcontrollers

  • 32-bit 3-8 stage in-order variant aimed at 50-250 Mhz microcontroller designs

  • Optional memory protection

  • Very low static power design

  • Fault Tolerant variants for ISO26262 applications

  • IoT variants will have compressed/reduced ISA support

I class processors

  • 64-bit, 1-4 core, 5-8 stage out of order, aimed at 200-1Ghz industrial control / general purpose applications

  • Devices aimed at networking applications will have dual-quad issue support

  • Other features – shared L2 cache, AXI bus, threading support

M Class processors

  • Enhanced variants of the I-class processors aimed at general purpose compute, low end server and mobile applications

  • Enhancements over I class – large issue size, quad-threaded, up to 8 cores, freq up to 2.5 Ghz, optional NoC fabric

S class processors

  • 64-bit superscalar, multi-threaded variant for desktop/server applications.

  • 1.2-3Ghz, 2-16 cores, crossbar/ring interconnect, segmented L3 cache

  • RapidIO based external cache coherent interconnect for multi-socket applications (up to 256 sockets)

  • Hybrid Memory Cube support

  • 256/512 bit SIMD

  • Specialized variants with FUs for database acceleration, security acceleration.

  • Experimental variants will be used as test-bed for the IIT-Madras Adaptive System Fabric project which aims to design a data-center architecture using NV RAM devices and unified interconnects for memory, storage and networking and leverages persistent memory techniques

H class processors

  • 64-bit in-order, multi-threaded, HPC variant with 32-100 cores

  • 512 bit SIMD

  • Interconnect TBD

  • Goal is 3-5 + Tflops (DP, sustained)

T class processors

  • Experimental security oriented 64-bit variants with tagged ISA

  • Single address space support

  • Decoupling of protection from memory management.

Processor Interconnect

The IIT-Madras CASL team is also developing a processor to processor cache-coherent interconnect to allow building of multi-socket S class systems. The interconnect is based on the RapidIO interconnect. The team is investigating a two tier approach whereby a MOESI/MESIF style scheme is used for 2-8 socket systems and a directory based scheme for larger configurations (max 256 sockets).

Flexible Design Approach

The approach is to built optimal, high performance, building blocks that can be shared among the variants and then add variant specific blocks as needed. The variants listed above are canonical references and the SHAKTI family will see device configurations that will be hybrids of the listed variants.

Where possible, Synopsys and Xilinx synthesis results will be made available for each module developed for the various processor variants.  Final design variant versions will contain the full BSV code, the generated Verilog code, testbenches, verification IP and FPGA support files.

Related Projects – Adaptive System Fabric

The SHAKTI effort is part of a larger effort to build complete systems. As part of this effort, IIT-M CASL is developing interconnects (optical and copper) based on 10xN & 25xN (10/25G per lane) RapidIO and a scale-out SSD storage system called LightStor. The final goal is to build a fabric called Adaptive System Fabric based on a combination of Hybrid Memory Cubes and RapidIO that will provide unified fabric support for compute, networking and storage. The source code repository for this project can be found at www.bitbucket.org/casl. As of this writing, both the RapidIO endpoint code and the SSD storage controller code are available on the repository.

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