Mirabilis Design joins RapidIO.org and announces VisualSim RapidIO Modeling Library: A system-level model of the RapidIO 10xN standard for rapid architecture exploration of computing, defense and networking systems

Mirabilis Design joins RapidIO.org to support wider adoption of the RapidIO standard with early and accurate architecture exploration

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Sunnyvale, CA. — November 6th, 2014— Mirabilis Design, the largest system-level modeling and simulation solution provider, announced today the release of the industry-first VisualSim RapidIO system-level modeling library. The product, VisualSim Architect is used extensively in many applications to architect systems, semiconductors and embedded software. Combining this RapidIO modeling library with the VisualSim modeling infrastructure, architects can explore the application of RapidIO fabrics in their current and future systems, test the feasibility of protocol extensions, and compute the latency and throughput across the full system containing the RapidIO interface. As a commitment to standards-based architecture exploration, Mirabilis Design has become a member of RapidIO.org. Mirabilis Design will support the technical evolution of the standard and integration of RapidIO based systems.

“Performance critical computing customers in communications infrastructure, datacenter analytics and Mil-Aero applications require open, multi vendor, industry standards based, low latency multiprocessor unified fabrics” said Rick O’Connor, Executive Director of RapidIO.org, “We are very pleased to have the support of Mirabilis Design Inc. as they join our strong RapidIO.org ecosystem with their very capable VisualSim based RapidIO modeling platform.”

The VisualSim Rapid IO library enables designers to measure the latency and effective throughput of the traffic and software tasks; compute the relative power consumption across architectures and test the reliability of the system. VisualSim Rapid IO library includes the functional, logical and timing accurate definitions of the 10xN RapidIO 3.0 specification. The main physical features include device interface, fragmentation, ingress queue, egress queue and a serial switch with multiple lanes. Signals include logical layer messages, flow control, acknowledgments, retry, errors and Read/Write activities.

The system models using VisualSim will include a combination of sensors, attenuators, processing units, memories, interfaces, buses, software behavior and traffic. Pre-built analysis reports include bandwidth, buffer occupancy, latency, throughput at the end-node and switches, data loss, and data flow trace. Other VisualSim modeling IP library include system-level interfaces: PCIe, PCI, Ethernet, Gigabit Ethernet, AFDX, TT Ethernet, CAN and FlexRay; SoC buses: AHB, APB, AXI and CoreConnect; and components: Processors, DRAM, Cache and DMA.

The VisualSim RapidIO library has reduced system level modeling and analysis time from months to days. One in particular, NASA JPL – Pasadena, CA, USA, used VisualSim on the Nexus project to compare different interfaces, to select Rapid IO as the best interface standard for space applications, and to identify the Rapid IO extensions. Numerous other companies have used our proven VisualSim RapidIO library to select the right system architecture to meet the requirements.

Mirabilis Design will be demonstrating the library capabilities in the RapidIO.org Booth at the Open Server Summit, Santa Clara (Nov 12-13, 2014) and at the Super Computing Conference, New Orleans (Nov 17-20, 2014).

Availability
VisualSim RapidIO Library is available now as an add-on to VisualSim Architect 14.3. The product is
supported on Windows, Linux, MAC OS and all other forms of UNIX.

 

About Mirabilis Design
Mirabilis Design is a Silicon Valley company, providing software solutions to identify and eliminate risk in
the product specification; accurately predict the human and time resources required to develop the
product; and improve communication between diverse engineering teams. VisualSim Architect is a
system-level modeling, simulation, and analysis environment using a complete set of libraries and
application templates that significantly improve model construction and analysis time. The environment
enables designers to rapidly converge to a design which meets a diverse set of interdependent time- and
power requirements. It is optimally used very early in the design process in parallel with (and as an aid to)
the development of the product’s written specification and long before an implementation (e.g., RTL,
software code, or schematic) of that product can even be started. Learn more at www.mirabilisdesign.com.

 

About RapidIO

The RapidIO unified fabric architecture, designed to be compatible with the most popular integrated host
processors, communications processors, and digital signal processors, is a high-performance, packetswitched,
interconnect fabric. RapidIO addresses performance critical computing needs in Data Center &
HPC, Communications Infrastructure, Industrial Automation and Military & Aerospace markets offering
high reliability, increased bandwidth, and low latency in an intra-system fabric. RapidIO provides chip-tochip,
board-to-board and shelf-to-shelf peer-to-peer connectivity at performance levels scaling to 100s of
Gigabits per second and beyond. RapidIO.org, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RapidIO unified fabric architecture. Learn more at
www.rapidio.org.
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Trademarks
Mirabilis Design, VisualSim and Mirabilis Design logo are trademarks of Mirabilis Design Inc.

 

Editorial Contact
Vaishnavi Shankar -Mirabilis Design Inc.
Email: info@mirabilisdesign.com

Mirabilis Design Inc.
1159 Sonora Ct, Suite 116
Sunnyvale, CA 94086
Tel: 408-844-3234

 

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