April 14 – 16, 2015
Santa Clara Convention Center
Santa Clara, California
Event Information »
RapidIO.org will be demonstrating:
- The RapidIO DCCN system: Open Source Data Compute and Networking System. This system is a processor agnostic, heterogeneous compute platform with 300Gb/S RapidIO switching. 268.8 GFlops/1U. Example configuration using 4 core intel i7-3612QE 2.1 GHz, 64GB of DDR3-1600 memory.
- Heterogeneous computing with low power ARM+GPU accelerators: The ARM+GPU node consists of 4 Nvidia Tegra Processors, aggregating to 1.5 Teraflops of computing with 140 Gbps of built in RapidIO interconnect. 6-12 Teraflops can be connected in a single 1U server, scaling to 400 ~Teraflops at Rack scale for high performance computing and low latency analytics applications. This scalable GPU acceleration node is suitable for Supercomputing at the edge of the wireless nework or in large clusters in the data center.
- Simulation Model of a Ethernet Cluster of RapidIO-based system: Simulate and analyse the system configuration to compute the end-to-end latency and throughput of a high-performance, real-time Application running on a distributed RapidIO-based compute server in an Ethernet network. Configuration will have a combination of 1, 10 and 100 Gbps Ethernet, 16X RapidIO interconnected board with 3Ghz 8-core processors with 64GB of DDR4 memory and 512 GB SSD.
- Verification of FPGA-based implementation using a virtual network model: Connect the hardware implementation on a Xilinx Zynq7000 FPGA board to a RapidIO backplane that is on a 1 Gbps Ethernet network virtual model. This demo will show how systems implemented on FPGA boards can be verified against a variety of realistic network architectures.
RapidIO session details
Session H-13. Design Issues 1 – 2:30 pm
Chairperson: Ed Sayre, Director Systems Engineering, Teraspeed Consulting Group
Devashish Paul, Sr Product Manager, IDT, “Scaling out Ethernet with an Industry Standard RapidIO Fabric”
Arlon Martin, Dir Marketing, Mellanox Technologies, “Copper and Optical Cable Options for 100GbE”
Rita Horner, Sr Technical Marketing Manager, “Enabling 40G/100G SoC Designs”
Jay Neer, Industry Standards Manager, Molex, “TBD”
Panel Session H-15. What Are the Keys to High-Speed Interface Design Today? 4 – 5 pm
Chairperson: Scott Feller, Assoc VP Product Marketing, Inphi
Joel Goergen, Distinguished Engineer, Cisco Systems
Ed Sayre, Director Systems Engineering, Teraspeed Consulting Group
Scott McMorrow, R&D Consultant, Teraspeed Consulting Group
John Lockwood, CEO, Algo-Logic
Ravi Thummarukudy, CEO, Mobiveil