RapidIO BFM User Group
The RapidIO Trade Association maintains a Bus Functional Model providing a compliance test suite that helps to reduce the overall verification effort. The BFM can be used to verify IP blocks, SoCs and system level designs.
Membership in the RapidIO BFM Users groups gives the following benefits
- Access to RapidIO BFM
- BFM technical support
- Participate in BFM Technical Working Group
RapidIO Bus Functional Model
The 10xN RapidIO BFM developed on behalf of the RapidIO Trade Association by Mobiveil supports RapidIO specifications 10xN (Gen3 version 3.0), 6xN (Gen2 versions 2.2 & 2.1) and 3xN (Gen1 version 1.3). The RapidIO BFM is developed in System Verilog and supports standard Universal Verification Methodology (UVM) and can be easily plugged in to any other UVM compliant verification components to extend a broader verification environment.
RapidIO BFM Features
- 1x, 2x, 4x 8x and 16x lane configurations.1.25 Gbaud, 2.5 Gbaud, 3.125 Gbaud, 5 Gbaud, 6.25 and 10.3125 Gbaud lane rates
- 66, 50 and 34-bit addressing on the RapidIO interface
- All types of packet formats
- Supports all types of IDLE sequences, Control and Status Symbols
- Scrambling/De-Scrambling and Encoding/Decoding
- Supports out of order transaction generation and handling
- Critical Request flow (CRF)
- Supports all transaction flows, with all priorities
- Test pattern generation at all protocol layers
- Error injection and error detection at all levels of protocol layers
- Provides Compliance Test Suite
- Functional Coverage
RapidIO BFM Architecture
In keeping with the layered structure of the RapidIO Specification, the RapidIO BFM is implemented using a layered architecture divided in to Logical, Transport and Physical layers. Also, a RapidIO monitor handles protocol checking and compliance with the RapidIO specification including providing hooks for implementing functional coverage, scoreboard and checker modules.
The user can constrain randomization at different levels and functional coverage helps gauging the effectiveness of the randomization. Detailed description of each Sequence is provided the BFM documentation and allows the user to extend and implement the required functionality.
Also, the RapidIO BFM includes a register model, which reflects the registers defined in the RapidIO Specification and provides coverage of these registers. The register model verifies the properties of the registers and it is also used by the scoreboard, monitor and functional coverage modules to collect and report functional coverage data. It provides detailed report log on the packets and symbols as well as a transaction tracker to track the transmitted and received packets and control symbols.
Multiple levels of verbosity are supported which eases the debugging effort. The RapidIO BFM can be easily integrated in to cycle-based or event-based simulation environments and can support latest versions of major simulation tools in the industry.
Contact us to join the RapidIO Bus Functional Model User Group.