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Steering & Sponsor Members
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The UC Berkeley ASPIRE project is a collaborative effort attacking the challenges of a new era, where pervasive application-specific specialization of software and hardware is the only path to computational efficiency. The rapid pace of evolution of complicated SoCs, both for mobile devices and datacenter server racks, requires rapid co-design and verification of hardware with software to avoid missing market windows. The computing industry must shift from the traditional model where transistor-scaling-driven performance improvements supporting horizontal layered architectures, to a new post-scaling world where vertical applications-to-hardware co-design is the key to improved efficiency. Some key work within the ASPIRE project is development of the RISC-V Instruction Set Architecture. RISC-V (pronounced "risk-five"), a new instruction set architecture (ISA) originally designed to support computer architecture research and education, is now set to become a standard open architecture for industry implementations. Learn more at www.riscv.org.
Data Center & HPC, Communications Infrastructure, Industrial Automation
Boards & Modules, Development Tools, Embedded Systems, Semiconductors, Software