RapidIO Interoperability


RapidIO Interoperability Testing by FET/RIOLAB


                                 

Leveraging the RapidIO® Trade Association’s common hardware interoperability platform (HIP) and interoperability specification checklist, RIOLAB, a division of Fabric Embedded Tools, is the world’s first independent RapidIO® Interoperability Lab.  A state-of-the-art, independent testing facility, RIOLAB provides the RapidIO eco-system with device interoperability and specification compliance testing to meet the growing needs of silicon vendors and OEMs. Originally launched in February 2006 the facility continues to receive overwhelming support from the RapidIO eco-system including Altera, Ericsson, Freescale Semiconductor, Integrated Device Technologies, Lucent Technologies, Texas Instruments, Tundra Semiconductor, Xilinx, and other members of the RapidIO Trade Association Steering Committee, industry experts, and OEMs.

“From its inception, the RapidIO Trade Association recognized that an independent test lab was a key milestone in the maturity of the standard that would facilitate widespread OEM design-ins,” said Tom Cox, executive director, RapidIO Trade Association.  “It was clear that an independent facility was required to achieve “Repeatable and Quantitative” results.”

RIOLAB addresses the need to ensure that components, systems and software using RapidIO® technology are compliant with the specification and have the ability to operate effectively together. Comprehensive interoperability testing increases the likelihood of achieving interoperability objectives in OEM designs and can result in significant savings in engineering time and costs.   The lab is the only facility in existence that provides commercial semiconductor vendors, FPGA and ASIC manufacturers with an unbiased common vehicle for demonstrating device interoperability and specification compliance to the RapidIO standard.

Visit Fabric Embedded Tools Corporation or RIOLAB for more information:  www.FETCORP.com, www.RIO-LAB.com

Interoperability Testing and the RapidIO Standard:

The Need for Repeatable and Quantitative Assessment

A White Paper by Jim Parisien,

President Fabric Embedded Tools Corporation

February 2008
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RapidIO Interoperability and the RapidIO Bus Functional Model

by RapidIO Trade Assoc./ GDA Technologies

             

Leveraging the RapidIO® Trade Association’s Bus Functional Model (BFM) and interoperability specification checklist, the RapidIO Trade Association offers its members the first step in ensuring the development  of RapidIO  Interoperability.  The RapidIO BFM was developed and donated to the RapidIO Trade Association, by Freescale Semiconductor.  The model is licensed to members and maintained under contract with GDA Technologies, the model is held in an 'Open Source' management agreement, which enables RapidIO to Sub-license the model to members. 
Continuous improvements to the model have been contributed by members and maintained by GDA technologies on behalf of RapidIO. Most of the semiconductor products today used the BFM in pre and post silicon verification.  Today the model includes the full functions of the 1.3 specification and a bus checker, the development of a RapidIO 2.0 model is nearing completion. 
To access the BFM requires a membership level of Regular ($9,500/year) or higher and the signed BFM sub-lisc agreement and $10,000/year fee for the maintenance of the model.

For more information on the model:  BFM whitepaper.

Or Contact us at the RapidIO Trade Association.