Frequently Asked Questions
- What is the RapidIO Trade Association?
- What are the benefits of joining the RapidIO Trade Association?
- What other major companies are involved in the RapidIO Trade Association in addition to ARM, Huawei, IDT, NXP Semiconductors and Texas Instruments?
- Are there fees associated with the RapidIO Trade Association membership, and if so, how much are they?
- What is RapidIO technology?
- Why choose RapidIO technology?
- What is the target market for RapidIO technology?
- What types of products are currently available on the market that are based on RapidIO technology?
- What makes the RapidIO architecture an ideal fabric technology?
- I don’t see references to RapidFabric on the web site anymore. Have you removed those features from the standard?
- How is RapidIO technology leveraged in AdvancedTCA?
- How is software development impacted by the RapidIO technology?
Q: What is RapidIO.org?
A: The RapidIO.org is a 501(c)6 nonprofit organization controlled by its members. The trade association directs future development, maintenance and promotion of the RapidIO interconnect as an open standard. Networking market participants are encouraged to join and thereby participate in the future of the RapidIO interconnect standard. The RapidIO architecture’s community-oriented development process has produced a true open standard. The members have elected a Steering Committee, which in turn oversees a Technical Working Group (TWG) and a Marketing Working Group (MWG). TWG responsibilities include providing a forum to coordinate specification development activities, managing the maintenance of the specification, and advising the TWG chair when amending policies and procedures. The MWG is responsible for all marketing and public communications activities for RapidIO, including press releases, trade show exhibitions, and conference presentations. The MWG also oversees the RapidIO web site, and plays the role of a Membership Committee for RapidIO.org. Both the TWG and the MWG also coordinates the activities of various Task Groups. RapidIO Fact Sheet
Q: What are the benefits of joining RapidIO.org?
A: Association members gain early access to the RapidIO architecture specifications. Membership also enables attendance at member meetings, participation in the development of the standard, and a license to the IP. RapidIO members also have optional access to a full design Bus Functional Model which is commonly used by members for chip and system design. For more information on joining the Trade Association, visit our page at Membership Page
Q: What other major companies are involved in RapidIO.org in addition to ARM, Huawei, IDT, NXP Semiconductors and Texas Instruments?
A:The RapidIO Trade Association includes leaders in embedded systems, including ARM, Huawei, IDT, NXP Semiconductors, Texas Instruments, Xilinx, Mercury, Altera along with many others that contribute to the definition and deployment of the RapidIO technology. See the list of member companies, at Member List
Q: Are there fees associated with RapidIO.org membership, and if so, how much are they?
A:Yes, the amount depends on the level of membership. Annual membership fees are $25,000 for the Steering Committee, $15,000 for Sponsoring Members, $9,500 for Regular Members, and $2,500 for Auditing Members. For more information please visit our Membership Page.
Q: What is RapidIO technology?
A: The RapidIO architecture is an electronic data communications standard for interconnecting chips on a circuit board and circuit boards using a backplane. The RapidIO architecture is designed to be used for the processor and peripheral interface where bandwidth and low latency are crucial. The RapidIO architecture is partitioned into a three-layer hierarchy of logical, transport, and physical specifications, which allows scalability and future enhancements while maintaining compatibility.
Q: Why choose RapidIO technology?
A: In addition to technical requirements, the high-performance embedded market requires an open standard interconnect. Currently, the market suffers from an overabundance of proprietary buses, requiring standard product and ASIC-based bridges to connect the various devices in the system. The RapidIO interconnect provides a common connection architecture for general purpose RISC processors, digital signal processors, communications processors, network processors, memory controllers, peripheral devices, and bridges to legacy buses. This efficient architecture benefits users by reducing cost, time-to-market, and complexity.
Q: What is the target market for RapidIO technology?
A: RapidIO technology is primarily designed for networking and communications equipment, enterprise storage, and other high-performance embedded markets. It addresses the networking industry’s needs for software transparency, greater reliability, and higher bandwidth in an “in-the-box interconnect.” The RapidIO interconnect provides higher bus speeds that allow chip-to-chip and board-to-board communications at performance levels ranging from 1 gigabit per second to 60 gigabits per second.
The RapidIO interconnect is targeted for use in environments where multiple devices must work in a tightly coupled architecture. As disk throughput increases in computing applications, so does the need for higher system throughput. Current applications are requiring higher bus performance, more device fan-out, and greater device separation. RapidIO can be used in such applications for transparent PCI-to-PCI bridging, allowing for a flattened architecture utilizing fewer pins and offering greater transmission distances. Many systems require the partitioning of functions into field replaceable units. These printed circuit boards can use RapidIO to achieve higher system level performance. RapidIO is also well suited for hot-swap applications, because its point-to-point topology enables the removal of devices with little or no electrical impact to neighboring devices or subsystems.
Q: What types of products are currently available on the market that are based on RapidIO technology?
A: The range of products is huge, extending from chips which enable the interconnect, to chips which are ready-made nodes on a RapidIO fabric, to off-the-shelf and custom IP which allows highly optimized designs, to board level products in a wide variety of form-factors and to chassis level systems, fully configured for the most demanding applications. See the Product Search to explore the ecosystem.
Q: What makes the RapidIO architecture an ideal fabric technology?
A: RapidIO architecture addresses the critical fabric requirements such as architectural independence, reliability and fault management, traffic management (classes of service, graceful degradation, support for thousands of flows), and widely scalable high performance. A viable fabric paradigm also requires the kind of ecosystem depth which is part of the RapidIO technology, containing processsors, DSPs, switches, a full range of IP and software and multiple deployed applications.
More about Quality of Service
Quality of service is an inherent part of the RapidIO specification, implemented directly in hardware and enabling traffic to be classified into as many as six prioritized logical flows. While the mechanism for forward progress in the fabric relies upon ordering rules at the physical layer to give responses higher priority, the degree to which prioritization results in lower average latency or jitter for a particular flow is specific to the actual implementation. For example, more aggressive switches might make ordering decisions based upon a flow’s priority, source, and destination ID fields while less aggressive designs might only utilize the priority field.
Qos is also affected by specific fabric arbitration policies. While the specification explicitly defines prioritized flows, developers are free to choose the particular arbitration policies to put into place to prevent starvation of lower-priority flows, such as the well-known leaky-bucket scheme. As even the least aggressive design must support these mechanisms, higher-priority flows are guaranteed to demonstrate better lower-average latency.
For applications requiring even more aggressive and effective QoS, advanced flow control and data plane capabilities are available. The RapidIO protocol defines multiple flow control mechanisms at the physical and logical layers. By managing physical layer flow control at the link layer, short-term congestion events are effectively managed for serial and parallel applications using both receiver- and transmitter-controlled flow control. Longer-term congestion is controlled at the logical layer using XOFF and XON messages which enable the receiver to stop the flow of packets when congestion is detected along a particular flow.
Receiver-only flow control, where the transmitter does not know the state of receiver buffers and the receiver alone determines whether packets are accepted or rejected based on receiver buffer availability, results in packets being resent, creating wasted link bandwidth. Additionally, ordering rules require a switch to send higher-priority packets before resending any packets associated with a retry, aggravating worst-case latency for lower priority packets.
Transmitter-based flow control avoids bandwidth wasting retries by enabling the transmitter to decide whether to transmit a packet based on receiver buffer status. Through receiver buffer status messages sent to the transmitter using normal control symbols, the transmitter is able to limit transmissions within the maximum number of buffers available at the receiver. In general, priority watermarks at the various buffer levels are used to determine when the transmitter can transfer packets with a given priority.
A third link-level mechanism is available within the parallel PHY specification which enables the receiver to throttle the packet transmission rate by requesting that the transmitter insert a selectable number of idle control symbols before resuming transmission of packets.
Revision 1.3 of the RapidIO specification achieves further efficiency and higher throughput through the introduction of data plane extensions. Since data plane fabrics can carry multiple data protocols, these extensions enable the encapsulation of virtually any protocol using a data streaming transaction type with a payload up to 64 Kbytes. Hardware-based SAR support is expected for most implementations, with up to 256 classes of service and 64 K streams.
The 2.0 revision of the specification builds on revision 1.3 capabilities, introducing a new 5.0 Gbaud and 6.25 Gbaud PHY, lane widths up to 16x, 8 virtual channels with either reliable or best-effort delivery policies, enhanced link-layer flow control, and end-to-end traffic management with up to 16 million unique virtual streams between any two endpoints.
The RapidIO protocol is a simple and efficient interconnect designed specifically for high-speed embedded applications and appropriate to serve as a system-level fabric. By implementing protocol processing in hardware, many quality of service and flow control mechanisms are an inherent part of the PHY, maximizing efficiency and throughput while minimizing latency and switch complexity. Backed by new data plane extensions which enable RapidIO switches to encapsulate virtually any data protocol, the RapidIO specification is an ideal interconnect technology, enabling developers to consolidate interconnect layers, as well as both control and data planes, into a single fabric, reducing cost while increasing overall system reliability.
Q: I don’t see references to RapidFabric on the web site anymore. Have you removed those features from the standard?
A: The RapidFabric sub-brand was a marketing initiative by the RapidIO Trade Association to ensure that the RapidIO standard was clearly identified as supporting fabric capabilities. RapidFabric specifically identified a subset of features in the RapidIO standard that were particularly suited for fabric connectivity. While the trade association is no longer using this sub-brand, all of the capabilities that it highlighted are still part of the RapidIO standard including:
- Flow Control Logical Layer Extensions Specification
- Data Streaming Logical Layer Extension Specifications
- Traffic Management
- Multicast Extensions Specifications
- Serial Physical Layer Specification
- Next Generation Physical Layer Specifications
Going forward, RapidIO continues to be the embedded fabric of choice and the only brand used by the trade association. RapidIO Specification 2.0 has been approved and Released.
Q: How is RapidIO technology leveraged in AdvancedTCA® designs?
A: The Advanced Telecom Computing Architecture (ATCA) is the name of the PICMG 3.X family of specifications that are targeted to requirements for the next generation of carrier grade communications equipment. PICMG 3.5 defines the rules and guidelines for implementation of RapidIO-based node and fabric cards based on the PICMG 3.0 standard. ATCA is based on the XAUI physical signal standard used for 10 Gigabit Ethernet. RapidIO also operates on XAUI and is the highest performance, true fabric technology available on ATCA. RapidIO technology offers a comprehensive standard for fabric connectivity in ATCA and much of the RapidIO ecosystem is organizing itself around the ATCA platform..
Q: How is software development impacted by the RapidIO technology?
A: Software development is independent of the RapidIO architecture, i.e., RapidIO technology is transparent to the existing software base. To software, the RapidIO fabric can look just like a traditional microprocessor and peripheral bus. RapidIO technology also bridges easily to PCI and PCI-X. These features allow users to mix legacy software and PCI chips with RapidIO chips, and without requiring special devices. RapidIO has allso a definition to encapuslate other protocals like Ethernet.