MM-1500
by
http://www.vmetro.com/category4168.html
- Contact:
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Nicole Renfro
Marketing Manager
- Description:
- Quad FPGA VXS/VITA 41 Carrier with two PMC/XMC sites and two Serial RapidIO ports on P0
Features
- Two CoSine 2VP100 System-on-Chips
- Two Xilinx Virtex-4 SX55 CoSine Companion Devices
- Two XMC/PMC sites
- VME64 master/slave interface
- 14 independent memory arrays with total bandwidth of over 40 GB/s
- Four embedded PowerPC processors
- Complete Serial RapidIO x4 connectivity
- VITA 41 format
- Rugged Air Cooled and Conduction Cooled versions
Description
The MM-1500 combines the industrys most powerful System-on-Chip, CoSine, with the application optimized architecture of an Othello VME carrier.
Mezzanine Sites
Mezzanine sites on the MM-1500 can support either PMCs or XMCs. Configured for PMC support, each PCI bus can operate in 32-bit or 64-bit PCI 2.3 mode at up to 66MHz or in 64-bit PCI-X mode at up to 133MHz. Configured for XMCs, the sites can support the Aurora protocol with four MGTs or Serial RapidIO x4.
Xilinx Virtex-4 SX55 and DSP Slices
The Virtex-4 SX55 is the largest device available in the SX family and offers the most DSP slices of any Xilinx FPGA. DSP slices are unique to the Virtex-4 FX, SX, and LX platforms. In the Virtex-II Pro and other FPGA families, only multipliers are offered thereby requiring all additions, subtractions, etc. to be implemented in logic.
CoSine Compute Nodes
The MM-1500 contains two independent CoSine Compute Nodes (CCNs). A single CCN is comprised of a CoSine Primary Device (Virtex-II Pro 2VP100), a CoSine Companion Device (Virtex-4 SX55) see CoSine and CoSine Companion Device Configurations and the following:
Two embedded PowerPC 405GP processors
One multi-ported primary DDR array, up to 1GB, for seamless bus translation between the mezzanine port and crossbar or backplane port
Two dedicated 128MB DDR arrays local to each PowerPC processor
Four independent 9MB QDR II SRAM arrays local to the SX55 for FPGA processing operations
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