Tsi721 PCIe Gen 2 to RapidIO Gen 2 Bridge

IDT

Contact:

Devashish Paul
Senior Product Manager

Description:

The Tsi721 is IDT's solution for hardware based PCIe Gen 2 to RapidIO Gen 2 protocol conversion in a bridging device. The Tsi721 converts from PCIe to RapidIO and vice versa and provides full line rate bridging at 20 Gbaud. Using the Tsi721 designers can develop heterogeneous systems that leverage the peer to peer networking performance of RapidIO while at the same time using multiprocessor clusters that may only be PCIe enabled. Using the Tsi721, applications that require large amounts of data transferred efficiently without processor involvement can be executed using the full line rate block DMA+Messaging engines of the Tsi721.
Device Features
x4 PCIe V2.1 to x4 S-RIO V2.1
Single port: x4, x2 or x1 support
1.25, 2.5, 3.125 and 5 Gbaud support
8 DMA and Messaging channels/engines each capable of supporting full 20 Gbaud I/O
8Kbyte packet buffering per DMA and Messaging Channel
20 Baud line rate performance for 64 byte or larger packets, max TLP payload 256 bytes, max block DMA 64 Mbyte
PCI Express non-transparent bridging for transaction mapping
Lane reversal
Automatic Polarity inversion for PCI Express
Typical power 1-2 W
Reach Support: 60 cm over 2 connectors
100, 125, 156.25 MHz S-RIO and PCIe Endpoint compatible clocking options
JTAG 1149.1 and 1149.6
13x13 mm FCBGA
Industrial and Commercial variants

Benefits

Use RapidIO's peer to peer networking performance with PCIe enabled microprocessors and Network Processors
Design Heterogeneous systems with RapidIO networks and PCIe networks
Execute large block data transfers without processor involvement for real time signal processing
No in house NRE required to develop bridging solutions with FPGA or ASIC
Save on FPGA related board space, power and BOM with Tsi721 solution
Use a mix of RapidIO and PCIe based payload processing cards in the same chassis
Map Block DMA transfers to RapidIO messages with dedicated DMA engine per messaging channel, ideal in a highly data intensive signal processing applications
Super deterministic performance and latency in embedded peer to peer systems compared to Ethernet.

Categories:

Intellectual Property > Bus Interfaces Intellectual Property > Endpoint Intellectual Property > Physical Interface Intellectual Property > RapidIO Endpoint Solutions Intellectual Property > Switch Fabric Semiconductors > ASSPs > Bridges Semiconductors > ASSPs > Switches Semiconductors > Bridge Chips Semiconductors > Switch Fabric Devices