MM-1600

VMETRO

Contact:

Nicole Renfro
Marketing Manager

Description:

Quad FPGA VPX/VITA 46 Carrier with 2x PMC/XMC sites and 4x Serial RapidIO ports on P1

- Two CoSine 2VP100 System-on-Chips
- Two Xilinx Virtex-4 SX55 CoSine Companion Devices
- Two XMC/PMC sites
- 14 independent memory arrays with total bandwidth of over 40 GB/s
- Four embedded PowerPC processors
- Complete Serial RapidIO x4 connectivity
- VITA 46 format
- Rugged Air Cooled and Conduction Cooled versions

MM-1600

The MM-1600 combines the industrys most powerful System-on-Chip, CoSine, with the application optimized architecture of an Othello VME carrier.

Mezzanine Sites
Mezzanine sites on the MM-1600 can support either PMCs or XMCs. Configured for PMC support, each PCI bus can operate in 32-bit or 64-bit PCI 2.3 mode at up to 66MHz or in 64-bit PCI-X mode at up to 133MHz. Configured for XMCs, the sites can support the Aurora protocol with four MGTs or Serial RapidIO x4.

Backplane Connectivity
In addition to having a VME320 2eSST interface, the MM-1600 is the first VME board to include complete on-board Serial RapidIO switch fabric connectivity, with four independent Serial RapidIO ports to the VITA 46 P1 MGT backplane connector per the VITA 46.3 draft standard.

Xilinx Virtex-4 SX55 and DSP Slices
The Virtex-4 SX55 is the largest device available in the SX family and offers the most DSP slices of any Xilinx FPGA. DSP slices are unique to the Virtex-4 FX, SX, and LX platforms. In the Virtex-II Pro and other FPGA families, only multipliers are offered thereby requiring all additions, subtractions, etc. to be implemented in logic.

CoSine Compute Nodes
The MM-1600 contains two independent CoSine Compute Nodes (CCNs). A single CCN is comprised of a CoSine Primary Device (Virtex-II Pro 2VP100), a CoSine Companion Device (Virtex-4 SX55) see CoSine and CoSine Companion Device Configurations and the following:

Two embedded PowerPC 405GP processors

One multi-ported primary DDR array, up to 1GB, for seamless bus translation between the mezzanine port and crossbar port to the backplane

Two dedicated 128MB DDR arrays local to each PowerPC processor

Four independent 9MB QDR II SRAM arrays local to the SX55 for FPGA processing operations

Categories:

Boards and Modules Boards and Modules > DSP/Image Processing Boards and Modules > I/O Embedded Systems > Embedded Computing Embedded Systems > Embedded Systems Embedded Systems > Image Processing Embedded Systems > Military and Defense Systems