RapidIO Connections - October 2002
In The News Spectrum Signal Processing's SDR-3000 Digital Transceiver SubsystemThe SDR-3000 is Spectrum Signal Processing's family of CompactPCI®-based digital transceiver subsystems, designed specifically for the implementation of high performance software defined radios. SDR-3000 utilizes Serial RapidIO™ to offer high-speed inter-board communications. As well, it can support hundreds of simultaneous transmit and receive channels, each with an independent air interface protocol. The SDR-3000 hardware consists of the following baseboards:
In order to achieve optimal data flows, standard interconnects are used:
Looking for a Native RapidIO Processor Solution? The latest RapidIO solution from Xilinx is the world's first PowerPCTM processor with a tightly integrated RapidIO interface. The solution includes the RapidIO 8-bit port Physical Layer Core fully compliant to the RapidIO Interconnect Specification v1.1, and a reference design to hook up the endpoint to the PowerPC's CoreConnect™ PLB implemented in a Xilinx Virtex-II ProTM FPGA. Designers can now have instant deployment of RapidIO. System architects can build their intelligent host controllers and peripherals based on the RapidIO interconnect with optimum performance. In a typical system, the processor spends most of the time waiting for data to come back from the interconnect. The tight integration between the PowerPC and the RapidIO interface allows balanced I/O and processor performance, thereby improving throughput flexibility and system integration. The RapidIO Processor Buffer provides an interface between the Xilinx PLB IPIF and the Xilinx RapidIO Physical Layer module. Figure 1 illustrates a block diagram of the typical use model for the RapidIO Processor Buffer. The module sits between the Xilinx PLB IPIF and the Xilinx RapidIO Physical Layer Core. The Processor Buffer provides the necessary clock domain transformation by supporting three independently clocked interfaces. 
Figure 1. RapidIO to PLB Bridge Block Diagram With this latest RapidIO solution from Xilinx, system architects can now build complete systems based on Virtex-II ProTM. They can now integrate several components such as PCI chipsets, Gigabit Ethernet MAC/PHY chips, memory controllers for multiple applications such as high performance DSP, control plane processing and distributed computing. The Xilinx RapidIO to PLB reference design and accompanying RapidIO to PLB application note is available as a free upgrade to the Xilinx RapidIO 8-bit LVDS Physical Layer core. More information is available at: www.xilinx.com/rapidio/rio_ppc.htm 
Figure 2. Xilinx Virtex-II Pro FPGA with RapidIO 8-bit Port Interface and IBM PowerPCtm 405 Proving Compatibility The following is provided by Dr. Michael Jones, Director of the Laboratory for Applied Logic, Department of Computer Science, Brigham Young University, Provo, Utah Email: jones@cs.byu.edu phone: 801 422-2217 The introduction of a new I/O standard, such as RapidIO™, requires a great deal of design and verification effort to increase efficiency while maintaining adequate compatibility with legacy standards, such as PCI. Formal, or mathematically well-defined, methods are a potentially valuable tool for verifying the compatibility of two I/O standards. The problem of reasoning about I/O standard compatibility is particularly well-suited for formal methods because I/O standards are intended to function in a wide variety of network configurations. While some of these configurations may be exhaustively analyzed using simulation methods, generalizing the correctness of one configuration to another configuration--or even better, all configurations--requires some form of reasoning. The Laboratory for Applied Logic (LAL) at Brigham Young University (Provo, Utah) is collaborating with a team at the Université Henri Poincaré (Nancy, France) to complete a pilot project that applies formal reasoning to a RapidIO verification problem. The verification problem is the problem of identifying all RapidIO network topologies for which unordered RapidIO messages can be used to implement PCI transaction ordering rules. The approach is to refine abstract models of PCI transaction ordering into concrete models of RapidIO behaviors. Refinement is the process of proving that a concrete system correctly implements an abstract system. This approaches combines the LAL's expertise in modeling PCI message ordering with the French team's knowledge of a constructive proof technique called incremental refinement. This pilot project will not only suggest best practices for applying formal reasoning to industrial-scale I/O standards, but will also provide a rigorously justified outline for linking PCI devices using RapidIO networks. Since the proof is constructive, the project will result in a precise description of network configurations and properties of a RapidIO-PCI bridge required to obtain compatibility. The results of the pilot project will be available in the scientific literature and on the web at lal.cs.byu.edu/  |
