RapidIO Connections - January 2003

In the News

Intrinsity Readies 2 GHz Embedded Processors FastMATH and FastMIPS Silicon Operating at 2 GHz, On Schedule for Sampling This Month

AUSTIN, Texas (December 3, 2002) - Intrinsity, Inc., the high-performance leader in embedded microprocessors,today announced that first silicon of its FastMATH Adaptive Signal Processor device and FastMIPS high-performance MIPS-based embedded processor operates at 2 GHz under nominal temperature and voltage conditions and is on schedule for December customer sampling.

Fabricated in Taiwan Semiconductor Manufacturing Company, Ltd.'s standard 0.13 µm LV CMOS process, FastMATH and FastMIPS processors benefit from Intrinsity's patented Fast14 Technology, which enables multi-GHz performance with low power from small design teams.

"With 2 GHz silicon, Intrinsity's engineering team has demonstrated the advantages of Fast 14 Technology in a complex microprocessor." stated Paul Nixon, president and chief executive officer, Intrinsity. "Our products prove that multi-Gigahertz processors can be delivered by a small chip team in less than eighteen months. We are pleased with the demand for samples from a variety of customers in several markets."

"It isn't often that a company can make a breakthrough technology claim like Intrinsity did last year and then back it up with product and in a timely fashion. Intrinsity has shown that it can execute and has the potential to be the performance leader in software-programmable signal processing markets," said Will Strauss, president of Forward Concepts.

Intrinsity's 2 GHz FastMATH microprocessor integrates an innovative matrix math unit with the MIPS-based processor architecture to deliver unprecedented real-time and math-intensive processing performance in applications that would otherwise require expensive FPGAs, banks of DSPs or power-hungry desktop CPUs. Unlike those products or exotic alternatives, the FastMATH microprocessor is fully-programmable, scaleable, and is supported by industry-standard software development tools.

RapidIO Interconnect Architecture Accepted as ECMA International Standard

Resulting ECMA-342 Standard will be Submitted to ISO/IEC for Fast Track Approval in 2003

Geneva, Switzerland and Austin, Texas _ January 20, 2003…In a significant standardization milestone for high-performance interconnect architectures, ECMA International today announced its new interconnect standard ECMA-342, which includes both parallel and serial versions of the RapidIO interconnect architecture developed by the members of the RapidIO Trade Association. This marks the first acceptance by an international standards organization of the next-generation of open interconnect standards designed to ensure reliability and systemlevel compatibility in high-performance networking, communications and embedded systems.

ECMA International was founded in 1961 and is dedicated to the standardization of information and communications systems. As part of its approval, ECMA will submit the approved standard to the ISO/IEC JTC1 for the latter’s Fast-Track process, involving a 6-month international ballot and comment period. The final specification is expected to be published by ISO/IEC as an international standard in autumn 2003.

Jan W. van den Beld, the Secretary General of ECMA International, said: “By accepting the RapidIO architecture, our TC42 Technical Committee ensured that the RapidIO interconnect was developed as an open standard, that it addresses the technical needs and concerns of the industry represented by ECMA International’s members, and ensures the interoperability, scalability, and reliability of I/O communications protocols needed in system-level communications. It is worth noting that acceptance was achieved rapidly and efficiently.”

Engineers worldwide, especially in Europe and Asia, look to ECMA-approved standards as they design new generations of high-performance embedded systems. Louis Francois Pau, general manager of Ericsson’s Core Network Products Divisions, noted: "Open public interconnect standardization is essential in the communications space, and embedded systems in general, to enable interoperability and reduced support costs for end users.

“It also triggers multi-vendor competition and thus performance enhancements for which RapidIO technologies already represent a timely leap forward at a time where bandwidth and service diversity put much higher demands on embedded hardware interconnect than can be handled by PCI or Ethernet."

The RapidIO parallel and serial interconnect architectures are open standards available for review and downloading at the RapidIO Trade Organization’s website www.rapidio.org. Also available at this website is information on system-enablement tools including RapidIO vendor product lists, synthesizable Verilog cores, analog physical layer cores, logic and protocol analyzers, operating system support, bus functional models, and a hardware interoperability platform.

The new standard is available on the ECMA International website www.ecma-international.org for review and downloading.

RapidIO Trade Association Drives New Mechanical Standards Through VITA and PICMG

Includes RMC Mezzanine Card Extensions to CMC and PMC Standards and Mapping Serial RapidIO™ to CompactPCI.2x Chassis

Austin, Texas _ January 20, 2003 - System designers will find it easier to implement high-performance parallel and serial RapidIO interconnects in a wide range of future embedded systems such as CMC and CompactPCI.2x, thanks to new mechanical specifications and efforts announced today by the RapidIO Trade Association. These specifications will be turned over to the VITA and PICMG organizations for completion and approval as standards.

Extensions to CMC/PMC Standards via VITA Specification work has been completed on the RapidIO Mezzanine Card (RMC) form factor, an extension to add parallel and serial RapidIO to the industry standard CMC (IEEE 1386) and PMC (IEEE 1386.1) form factors for I/O mezzanine cards. These RMC specifications have been transferred to VITA for completion and approval as a VITA standard in the near future. Further options for high-performance embedded systems will come from VITA’s ongoing development efforts on the switched serial standard VXS and its mapping of Serial RapidIO within the VME chassis (VITA 41.2).

Ray Alderman, Executive Director of VITA, is “looking forward to leveraging the detailed work completed by the RMC Task Group to rapidly create a high speed serial interface standard for today’s PMCs and Processor PMCs (PrPMCs). Embedded designers can therefore use the popular IEEE1386.1 (PMC) compatible form factor updated with the high-end interface speeds required by radar, sonar, medical imaging, and of course telecommunications applications.”

Ray continued, “OEMs can design carriers with sites for today’s standard PMCs/PrPMCs that are already compatible with upcoming VITA-42 serial interface mezzanines – a real space-saving solution during the transition to VITA-42 interface speeds. And, of course, Serial RapidIO will be a key alternative in upcoming VITA-41 VXS products.”

Thomas Nygaard, Chief Technical Officer and co-founder of VMETRO, adds that the RMC card definition and VITA efforts “pave the way for RapidIO as the switch fabric architecture of choice for next generation high-performance embedded systems.”

Randy Banton, chair of the RMC Task Group and engineering director at Mercury Computer Systems, noted “the broad participation of large and small RapidIO member companies whose efforts will enable various product vendors to supply one or more PMC and RMC compatible mezzanine locations on a common carrier.”

CompactPCI 2.x and Advanced TCA Platform Mapping via PICMG
Specification work has begun for mapping Serial RapidIO into the CompactPCI 2.x chassis. In addition, future efforts will include mapping full-speed Serial RapidIO to the Advanced TCA™ platform recently announced by PICMG for next-generation telecommunications equipment, with its new form factor and switch fabric based architecture. The Serial RapidIO to CompactPCI 2.x chassis specification will be submitted through companies who are members of both the RapidIO Trade Association and PICMG.

Richard Somes, PICMG Technical Director said: “The mapping of 1.25 Gbaud Serial RapidIO onto available PICMG 2.x platform will provide another point in the continuum of performance between PICMG 2.16 and PICMG 2.20. It promises to increase the versatility and broaden the range of addressable applications. We also look forward to a proposal to map full-speed serial RapidIO onto the AdvancedTCA platform, which is already optimized for the required link technology.” Frank Van Hooft, system engineering manager at Spectrum Signal Processing, points out that “using RapidIO within CompactPCI for moving real-time data is a powerful combination for many commercial and defense applications. For these reasons, RapidIO is gaining broad market acceptance.”

RapidIO Momentum
Sam Fuller, president of the RapidIO Trade Association, said: “RapidIO made great progress last year with the publication of the Serial RapidIO standard as well as increasing our membership to more than 50 companies worldwide. The momentum behind RapidIO continues with these mechanical specifications as well as ECMA International’s acceptance of RapidIO as ECMA Standard 342. All of this gives designers global standards to design a diversity of platforms to implement high-performance embedded systems. We expect 2003 will be a major breakout year with new RapidIO-enabled chips, systems and tools that will firmly establish RapidIO as the leading high-performance interconnect solution.”

The RapidIO parallel and serial interconnect architectures are open standards available for review and download from the RapidIO Trade Association’s website www.rapidio.org. Also available at the website is information on system-enablement tools including RapidIO vendor product lists, synthesizable Verilog cores, analog physical layer cores, logic and protocol analyzers, operating system support, bus functional models, and hardware interoperability platforms.