RapidIO Connections - April 2003

In the News

Release of Serial RapidIO Bus Functional Model Underscores Commitment to International Standards and Interoperability

Smart Networks Developer Forum, Dallas, Texas (March 24, 2003) - Designers can verify Serial RapidIO™ system interoperability using the just-released Serial RapidIO bus functional model from the RapidIO Trade Association. This software module complements the hardware interconnect platform (HIP) specification issued last year and further underscores the Association’s commitment to meeting the engineer’s need for open, internationally approved standards as they design next-generation, high-performance embedded systems. The Serial RapidIO bus-functional model was developed by Motorola and licensed to the RapidIO Trade Association for use by its members.

"Motorola is committed to the RapidIO interconnect architecture and we are pleased to make this important verification model available to RapidIO member companies," said David Perkins, corporate vice president and general manager of Motorola’s Networking and Computing Systems Group. “Device interoperability is an important design consideration and the RapidIO Trade Association is unique in providing this common reference model to add a level of confidence to device and system designers design efforts.”

Louis Francois Pau, general manager of Ericsson’s Core Network Products Division, said: “The very availability of a serial bus functional model is essential for telecommunications equipment vendors to speed up the adoption of RapidIO standards-compliant architectures and devices from different vendors in their systems and sub-systems. It is also a big step in enhancing and easing interoperability testing to the best advantage of operators and other users of such systems.”

Serial RapidIO has been selected by leading DSP and system vendors for serial backplane connections for its minimization of pin-count, ease of design, and greater performance and flexibility. “We are pleased that the RapidIO Trade Association continues to deliver on its commitment of broad-based interoperability among different suppliers by providing the serial bus functional model to all of the member companies,” said John Pitrus, product line manager of wireless infrastructure at Analog Devices. “We are planning to take full advantage of the model because the RapidIO interconnect architecture is leading the industry in terms of speed, flexibility and suitability for high-performance embedded systems where our DSPs are typically used.”

Sam Fuller, president of the RapidIO Trade Association, adds: “Motorola’s contribution illustrates the collective commitment of all our trade association members to make RapidIO the embedded interconnect performance leader. RapidIO is available now, unlike other embedded standard efforts that are still in the development stage. The models and our ISO standardization efforts offer engineers proof that RapidIO-based systems work together exactly as specified.”

ECMA International adopted parallel and serial RapidIO as the ECMA-342 interconnect standard in January, 2003. As part of its approval, ECMA has submitted the approved standard to the ISO/IEC JTC1 for the latter’s Fast-Track approval process, involving a six-month international ballot and comment period. The final specification is expected to be published by ISO/IEC as an international standard in autumn, 2003.

Bus functional models for both the serial and parallel RapidIO physical layer interfaces are available to member companies of the RapidIO Trade Association at www.rapidio.org. The models are written in C and can be interfaced to popular simulation environments. Also available at the website is information on system-enablement tools including RapidIO vendor product lists, synthesizable Verilog cores, analog physical layer cores, logic and protocol analyzers, operating system support, and hardware interoperability platforms.

Tundra Semiconductor Leads RapidIO Market with Launch of First Commercially Available Products

Dallas, Texas, March 24, 2003 - Tundra Semiconductor (TSX:TUN), the leader in System Interconnect today announced the first commercially available RapidIO System Interconnect products: the Tundra Tsi400™ RapidIO to PCI-X Bus Bridge and the Tundra Tsi500™ RapidIO Multi-port Switch.

RapidIO technology - supported by communications giants such as Alcatel, Motorola, IBM, Lucent Technologies and Ericsson - delivers the performance required in next-generation systems for both communications and storage companies. It takes advantage of the characteristics of new process technology to give customers an outsourced interconnect solution that is easy to integrate and shortens time to market.

Tundra is the first company to build System Interconnect devices for RapidIO. This significant milestone strengthens the leadership position Tundra has achieved in the RapidIO market.

"Today's launch is the culmination of extensive investment in research, development and testing," said Jim Roche president and CEO of Tundra. "These products respond to the need for intelligent, off-the-shelf System Interconnect solutions. Next generation systems must demonstrate robust and flexible performance to support a myriad of embedded applications. The launch of the Tundra Tsi400 and Tsi500 makes this a reality and opens the door to a new and expanding RapidIO market for Tundra."

Motorola, as part of an agreement announced in September 2000, collaborated with Tundra to support RapidIO product development. "Tundra has driven the RapidIO standard and brought RapidIO System Interconnect devices to market first," said David Perkins, corporate VP and general manager, Networking and Computer Systems Group, Motorola Semiconductors. "These next-generation System Interconnect products have opened up a new growth market for Tundra and Motorola."

The RapidIO Trade Association is also closely involved in driving the RapidIO standard. "Tundra - a founding member of the RapidIO Trade Association - continues to provide leadership in the advancement and realization of the standard," said Sam Fuller, president of the RapidIO Trade Association. "The role Tundra continues to play in RapidIO roll-out is pivotal."

Tundra has been invited to demonstrate these products during the opening keynote address at the Motorola Smart Networks Developer Forum this week in Dallas, Texas.

Motorola Demonstrates PowerQUICC™ III Communications Processor at Smart Networks Developer Forum

Motorola Live Demonstration of Next Generation MPC8560 Integrated Communications Processor Showcased for Customers and Smart Networks Alliance Partners

SMART NETWORKS DEVELOPER FORUM, DALLAS - March 26, 2003 - The revolution in high-performance communications processing has begun. Motorola, Inc. (NYSE:MOT) today demonstrated live silicon functionality of the next generation PowerQUICC™ III processor containing a PowerPC® core to a packed house at its Smart Networks Developers Forum (SNDF) taking place in Dallas, Texas.

"In addition to reaching today's major milestone of demonstrating PowerQUICC III silicon, Motorola-in concert with its alliance partners-is delivering a comprehensive ecosystem that will benefit networking equipment customers who have experienced significant reductions in R&D spending during the last two years," said Eric Mantion, senior analyst for In-Stat/MDR. "The PowerQUICC III processor offers the most versatile and sophisticated communications processor architecture in the industry. This demonstration is a momentous accomplishment for this very successful SNDF."

"The MPC8560 communications processor raises the bar for Motorola and our customers in terms of performance, integrated features and functionality," said David Perkins, corporate vice president and general manager of Motorola's Networking and Computing Systems Group. "We are seeing a very positive response from several of the world's largest communications equipment manufacturers. The PowerQUICC III processor family is shaping up to be the most successful PowerQUICC product line we've ever introduced."

"As the first company to offer test and measurement support for PowerQUICC III, Tektronix is proud to participate in this first silicon demonstration here at SNDF," said David Bennett, general manager, Logic Analyzer Products at Tektronix. "With Tektronix' new TMS568 PowerQUICC III support package for the TLA700 Series logic analyzers, Motorola and its early adopter customers are able to test the logic of MPC8540/8560 processor-based designs with unprecedented speed, visibility and signal integrity."

The comprehensive PowerQUICC III System-on-Chip (SoC) architecture features an array of leading industry standards and advanced Motorola technologies, including a high-performance Book E PowerPC e500™ core, a 256KB on-chip L2 cache memory array, an enhanced Communications Processor Module (CPM), RapidIO™ interconnect technology, dual Gigabit Ethernet interfaces, and support for Double Data Rate SDRAM (DDR SDRAM) and PCI/PCI-X.

Texas Instruments Becomes Steering Committee Member of the RapidIO Trade Association

Austin, Texas (April 2, 2003) – Texas Instruments (NYSE:TXN), the leader in real world signal processing, and the RapidIO Trade Association today announced that TI has become a member of the RapidIO Steering Committee, effective immediately. In this role, TI will help drive the technical standards and marketing efforts within the trade association, along with eight other steering committee member companies, to make RapidIO the embedded interconnect performance leader. Currently, there are more than 50 members of the association, of which TI has been a member since 2001.

"RapidIO meets the performance, reliability and interoperability requirements of next-generation embedded DSP applications such as wireless infrastructure communication systems,” said Dave Shepard, general manager for TI’s wireless infrastructure products. “It's an internationally certified, open standard that is available today. We look forward to making RapidIO the compelling choice for signal-processing intensive applications."

Sam Fuller, president of the RapidIO Trade Association, said: “Our trade association has attracted the world’s leading silicon, software, design, test, and systems companies whose collective goal is embedded interconnect performance leadership. Texas Instruments participation at the steering committee level clearly demonstrates the momentum behind RapidIO and will accelerate its global deployment.”

Texas Instruments joins the other members of the steering committee which includes Alcatel, EMC2, Ericsson, IBM, Lucent Technologies, Mercury Computer Systems, Motorola, and Tundra Semiconductor.

The RapidIO parallel and serial interconnect architectures are open standards available for review and download from the RapidIO Trade Association’s website www.rapidio.org. Also available at the website is information on system-enablement tools including RapidIO vendor product lists, synthesizable Verilog cores, analog physical layer cores, logic and protocol analyzers, operating system support, bus functional models, and hardware interoperability

Mercury Computer Systems Unveils First RapidIO Multicomputer System

ImpactRT 3100 Delivers Quantum Leap in Processing and Communication Bandwidth

CHELMSFORD, Mass. - March 31, 2003 - DALLAS, TX - March 31, 2003 - Mercury Computer Systems, Inc. (NASDAQ:MRCY), announced today at the Global Signal Processing Expo (GSPx) its ImpactRTTM 3100, the first scalable, high-performance, signal and image processing system based on the open-standard RapidIO® interconnect architecture. Combining next-generation PowerPC® microprocessors with AltiVec™ technology and the RapidIO communications switch fabric, the ImpactRT 3100 system more than quadruples the performance of the current ImpactRT systems while maintaining backward compatibility with existing application software.

"The ImpactRT 3100 system combines Mercury's recognized leadership in multiprocessor architecture and software with the most powerful emerging technologies to create a new benchmark in embedded computing power," said Richard Jaenicke, director of product marketing, Mercury Computer Systems, Inc. "This system demonstrates that RapidIO in Mercury's computing architecture provides a clear growth path for customers demanding ever greater processing power, and sets a new standard for cost-optimized performance."

Each chassis in the ImpactRT 3100 system scales to 2.4 TeraOPS of processing power, as compared to the current ImpactRT S500 system that scales to 0.5 TeraOPS. The new ImpactRT 3100 system balances the massive processing power with up to 10 GB/s of input data and 60 GB/s of interprocessor bandwidth to solve the most demanding commercial applications in markets such as medical imaging and semiconductor imaging. Communications bottlenecks are eliminated with a RapidIO communications link to each processor node.

Mercury's industry-leading multiprocessor graphical development and debugging tools, such as the TATLTM multiprocessor trace analysis tool and library, enable the development of complex, real-time applications on the ImpactRT 3100. Multiprocessor communication libraries and algorithm libraries convert 'islands of processing power' into a single, parallel processing system that increases throughput and reduces latency. Software for the ImpactRT 3100 system is compatible with Mercury's current RACE++ Series software, maintaining the existing application programming interfaces (APIs) and development tool chain.

The ImpactRT 3000 product line is the first in a series of RapidIO-enabled product lines from Mercury. Based on the CompactPCI form factor, ImpactRT systems are optimized for cost-effective performance in commercial environments. Future systems will address applications in harsh environments and those requiring other form factors.

Mercury's ImpactRT 3100 system will ship in the second quarter of this calendar year to early access customers and will be more broadly available in the second half of this calendar year.

Denali Software Joins RapidIO Trade Association

Austin, Texas and Palo Alto, Calif. (April 15, 2003) – The RapidIO Trade Association and Denali Software, Inc., the leading provider of semiconductor intellectual property (SIP) and electronic design automation (EDA) tools for chip interface design and verification, today announced that Denali has become a member of the RapidIO Trade Association and is taking an active role in the definition of the flow control specification. An internationally certified, open-standard that's available today, RapidIO is the embedded interconnect performance leader for next-generation communications and networking systems applications.

David Lin, vice president of business development, said: "Denali is the industry leader in design and verification solutions for complex chip interfaces. We're seeing great interest in RapidIO from our customers who depend on Denali software as they develop and verify advanced embedded systems designs. We look forward to leveraging our infrastructure and enabling RapidIO-based systems for our customers in the near future."

Steve Curtis, RapidIO steering committee representative from IBM Microelectronics and manager of embedded PowerPC standard products, adds: "Participants like Denali Software bring the necessary expertise in interface design and bus functional modeling to the RapidIO Trade Association. Their active involvement can help give designers and vendors further confidence in the system interoperability and growing pervasiveness of RapidIO-based embedded systems."

Sam Fuller, president of the RapidIO Trade Association, said: "Denali's membership demonstrates the momentum behind RapidIO. Our members are offering now the design tools, silicon, testing, and systems that are enabling profitable, early-to-market, performance-differentiated embedded systems."

The RapidIO parallel and serial interconnect architectures are open standards available for review and download from the RapidIO Trade Association's website www.rapidio.org. Also available at the website is information on system-enablement tools including RapidIO vendor product lists, synthesizable Verilog cores, analog physical layer cores, logic and protocol analyzers, operating system support, bus functional models, and hardware interoperability platforms.