RapidIO Connections - September 2003
Membership: Looking for a (re)Configurable RapidIO solution?
MathStar is a fabless semiconductor company developing fast, flexible, low-cost reconfigurable logic platform chips called Field Programmable Object Arrays (FPOA)™. These devices offer the performance, features and re-programmability required to integrate or bridge RapidIO to many popular system functions or legacy interfaces found in DSP and networking communication systems.
MathStar FPOA technology supports both parallel and serial RapidIO physical layers. The parallel physical layer is supported by configurable 8/16 bit LVDS interfaces which can be clocked up to 800MHz (1600MT/s) providing 3.2Gbyte/sec of peak bandwidth. The serial physical layer is supported by 1-4.25 Gbit/sec configurable SerDes I/O, providing a complete PMA and PCS (8B/10B) solution in hardware. Regardless of the physical layer choice, the transport and logical layers of RapidIO are implemented in the 1GHz (re)Configurable Silicon Object™ fabric.
The FPOA Silicon Object fabric consists of 16-bit medium-grained devices like Arithmetic Logic Units, Multiply-Accumulators, Pattern-matching CAMs, Register Files, CRCs, and Truth Functions. The FPOA architecture integrates hundreds of the 16-bit data plane objects with a sideband control plane. This two-level homogenous communications structure of Nearest-Neighbor and PartyLineTM interconnect all operate synchronously at 1GHz, delivering unprecedented performance in a field programmable device.
FPOA applications are developed using MathStar's NoGates™ design flow providing a dramatic simplification from conventional synthesis and gate level layout and timing closure based flows. Applications are developed, simulated and verified in a SystemC environment utilizing cycle accurate models of all FPOA resources. Once complete, the design is floorplanned and a bit-stream is generated for programming the device via a PROM or the JTAG interface. For more information visit www.mathstar.com.
