RapidIO Connections - September 2003

In the News

New Report Predicts RapidIO™ To Lead Bus Architecture Wars

AUSTIN, Texas - August 25, 2003 - In its recently released report, the consulting firm Metz International predicts that RapidIO, the high performance embedded interconnect architecture, will lead the emerging bus architecture "wars" through the end of the decade. The value of RapidIO ports shipped is expected to total more than $400 million in 2007, versus an estimated $200 million for the competitive Advanced Switching interconnect architecture.

"RapidIO is clearly out of the starting gate early, with software, silicon, test and RapidIO-based computers on the market already," says report author Ernie Bergstrom of Crystal Cube Consulting, who co-authored the report with John G. Metz of Metz International. "Our analysis indicates it will be the embedded market leader in terms of ports shipped between now and 2007. The RapidIO Trade Association's recent decision to add data plane extensions clearly demonstrates its intentions to keep RapidIO at the leading edge of communications and other embedded applications."

The report, entitled "Bus Wars Episode II: Clash of the Titans," is available for purchase at the Metz International website located at www.metzinternational.com.

The RapidIO interconnect architectures are open standards available for review and downloading from the RapidIO Trade Association's website, www.rapidio.org. Also available at the website is information on system-enablement tools including RapidIO vendor product lists, synthesizable Verilog cores, analog physical layer cores, logic and protocol analyzers, operating system support, bus functional models, and hardware interoperability platforms.

RapidIO™ Expanding to High-Speed Data Plane Applications, PICMG® 3.5 Spec Defines RapidIO on AdvancedTCA™

Austin, Texas - June 16, 2003 - In an important roadmap extension of the RapidIO interconnect architecture, the RapidIO Trade Association today announced plans to expand its application focus to fully cover data plane applications for telecommunications networks. The planned extensions will enable lower-cost standards-based products such as multiprotocol switches, 10 gigabit Ethernet switches, edge routers, SAN switches, DSLAMs and IP service switches. The resulting specifications will foster the replacement of current proprietary data fabrics with an open-standard technology, reducing development costs and accelerating time to market, through the adoption of off-the-shelf components. The extensions, expected to be finalized in early 2004, will retain compatibility with existing RapidIO switch and endpoint products based on the layered RapidIO architecture.

"This extension has intriguing system-level and chip-level implications," states Eric Mantion, senior analyst for the market research firm In-Stat/MDR. "It will enable new system configurations between blade servers, network and storage systems, as well as new enterprise telecom applications. It also lets designers 'massively cluster' many chips or cores within a system, since RapidIO is also a chip-to-chip interconnect."

In a separate effort, the PICMG® 3.5 subcommittee is being re-organized to map the full range of RapidIO protocols onto the AdvancedTCA™ platform architecture rather than limiting its attention to data plane oriented protocols alone. A PICMG 2.18 subcommittee, tasked with mapping RapidIO onto the CompactPCI® platform, was also recently approved.

"Extending RapidIO to an even broader range of data plane applications while carrying forward RapidIO's best-in-class control plane features creates a very compelling unified open interconnect architecture," says Dave Wickliff, RapidIO steering committee representative from Lucent Technologies. "Leveraging RapidIO standards onto AdvancedTCA via PICMG 3.5 will extend this open interconnect into the important box-level telecommunications platform. RapidIO provides an interconnect architecture that can homogenously span a complete platform: backplane, boards, mezzanines, and devices."

Richard Somes, PICMG Technical Officer, adds: "With the change in charter for the PICMG 3.5 subcommittee, RapidIO becomes a valuable High Speed Fabric option for the AdvancedTCA platform. The cooperative effort between PICMG and the RapidIO Trade Association adds to the considerable momentum behind the AdvancedTCA family of specifications for next generation carrier grade equipment."

The RapidIO data plane extension leverages efforts completed earlier by the RapidIO Trade Association, as well as work contributed by the Advanced Fabric Interface (AFI) working group.

"There was significant synergy between the goals of the Advanced Fabric Interface working group, and the vision for RapidIO, " says Chuck Hill, system architect with the Motorola Computer Group in Tempe, Arizona, who spearheaded the AFI effort. "An open standard with data plane features is essential to increased penetration of commercial off-the-shelf systems into certain telecom applications."

"This extension benefits current as well as future RapidIO users as it will impact all future data plane applications," says Sam Fuller, president of the RapidIO Trade Association. "We have strong interest from current and prospective members on this initiative. It's also further evidence of RapidIO momentum. It's an internationally certified standard and products based on RapidIO are available today. Designers around the world are using RapidIO's design software, silicon, simulation, verification, and testing tools to create high-performance embedded systems."

The RapidIO interconnect architectures are open standards available for review and downloading from the RapidIO Trade Association's website, www.rapidio.org. Also available at the website is information on system-enablement tools including RapidIO vendor product lists, synthesizable Verilog cores, analog physical layer cores, logic and protocol analyzers, operating system support, bus functional models, and hardware interoperability platforms.

MathStar Alters Field Programmable Device Landscape with Field Programmable Object Array (FPOA)™ Architecture

Minneapolis, MN - June 16, 2003 - MathStar, an innovator in high-performance semiconductors, today revealed architectural details of the company's Silicon ObjectsTM technology. The company's new family of products based on Silicon Objects, called Field-Programmable Object Arrays (FPOA), will offer a solution to companies caught between the vexing issues of development cost hurdles with 130nm ASICs and performance limitations of conventional FPGAs. The FPOA product family gives design teams flexible field re-programmability with deterministic 1GHz clock performance and attractive unit costs. In addition to the unprecedented performance achievable with FPOA architectures, the Silicon Objects based NoGates design process dramatically simplifies conventional chip design flows. With NoGates, cycle-accurate C-based functional models are directly mapped into the FPOA architecture, eliminating synthesis and associated gate-level place and route timing closure steps.

"MathStar has developed an ideal solution to both the financial and technical challenges of high-performance chip development in the 130nm world and beyond. FPOA architectures deliver the best combination of FPGA programmability, ASIC performance, no masks to buy, and dramatically lowered design tools requirements," stated Tim Rhodes, MathStar's Marketing Director.

Silicon Objects are 16-bit medium-grained devices like Arithmetic Logic Units, Multiply-Accumulators, Pattern-matching CAMs, Register Files, CRCs, and Truth Functions. The FPOA architecture integrates hundreds of the 16-bit data plane objects with a sideband control plane in a two-level homogenous communications structure of nearest-neighbor and PartyLine interconnect. The objects are synchronously clocked at 1GHz, delivering unprecedented performance in a field-programmable device.

MathStar will target applications domains using customized mixes of object types, on-chip memory resources, and high-performance I/O. Initial target applications will include extreme DSP and wire speed packet processing and aggregation applications in 10Gbps networking and storage equipment markets.

The synchronous nature of the architecture and the granularity of the objects combine to enable chip designers to develop their applications without regard to gate-level synthesis or timing closure issues. This eliminates two significant iteration loops in conventional design flows which commonly have significant impact on development schedules. With FPOA devices and the NoGates design flows, teams will be able to develop applications in weeks as opposed to months. In addition, like FPGAs, there is no fabrication cycle delay.

Equally revolutionary to the FPOA architecture, MathStar's NoGates design tool flow is a dramatic simplification from conventional synthesis and gate-level layout and timing closure based flows. Using the NoGates flow from MathStar and the company's tools partners, synthesizers and Place & Route tools are a thing of the past. Customers can focus almost exclusively on design functionality using high-performance cycle-accurate simulation models. MathStar's new FPOA based NoGates design tool flow is available early Q3 for customer evaluation. Product samples will be available in the fourth quarter.

MathStar, www.mathstar.com, designs and develops ultra-high performance semiconductors for networking, storage, signal processing, and reprogrammable platform markets. Founded by communications industry veteran Douglas M. Pihl, MathStar is a development stage company headquartered in the Minneapolis, MN metropolitan area.

For more information about MathStar, Inc., please visit the company's website at http://www.mathstar.com or email us at info@mathstar.com.