RapidIO Connections - December 2003
Important new RapidIO White Papers Available! Implementing the RapidIO Interconnect Specification A new white paper that describes the major trade-offs to be made in implementing the RapidIO interconnect specification is now available. This paper, written by an experienced Motorola design engineer, presents the design tradeoffs associated with implementing RapidIO. It provides a detailed description of a typical RapidIO endpoint implementation architecture. The paper does not assume a prior knowledge of the RapidIO interconnect specification. The implementation complexity of a RapidIO endpoint is found to be on the order of 100K gates of logic, which is significantly less than competitive technologies. The white paper can be found on the AnalogZone website at: Enter the Inner Sanctum of RapidIO Since its inception, the RapidIO specification has evolved and undergone a number of enhancements to meet the ever more sophisticated control and data plane interconnect needs of today's communication designers. This two-part set, written by Greg Shippen, Chair of the RapidIO Trade Association Technical Working Group, provides an updated view of the specification, highlighting traditional and new RapidIO capabilities. This white paper is available on the CMP website at:
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