RapidIO Connections Newsletter - Spring 2005
Member Connection:The Need for Optimized Bridging Between PCI™ and Serial RapidIO® RapidIO has distinct advantages over alternative architectures for distributed multiprocessor systems. Instead of a hierarchal, spanning tree topology, such as found with PCI-X™ and PCI-Express™, RapidIO supports peer-to-peer communications with dual-star, mesh, daisy-chained or tree topologies. Other architectures, such as PCI, are based on the assumption of a central host and a common memory map shared among all devices. But many embedded systems have multiple distributed processors that can benefit greatly from having direct access to multiple different endpoints (I/O, memory controllers, or other processing elements). RapidIO fulfills these embedded requirements by providing highly efficient data transfers in part through its provisions that enable multiple devices to share memory globally. With its hardware-based message passing architecture that was specifically designed for these types of distributed systems, higher overall performance can be realized with reduced complexity. The Necessity to Bridge PCI and RapidIO Because the commercial server markets drive the design and production of many high performance I/O peripherals (fibre channel, Gigabit Ethernet, Infiniband, etc.), providers of I/O silicon often select PCI/PCI-X/PCI-Express as the digital interface for their chipsets. These various server markets also facilitate a large breadth of options for I/O connectivity (graphics, video, firewire, USB, etc.) and long distance interfaces to larger network infrastructures, e.g. ATM to WAN. Despite RapidIO’s many technical advantages for embedded systems, it is likely that many of the silicon providers of these I/O peripherals will continue to offer devices with PCI/PCI-X/PCI-Express interfaces because they primarily target commodity platforms. However, for embedded system designers, availing of the latest I/O peripherals and other related silicon produced for high end commercial servers has and will continue to be a definitive requirement. It provides the ability to leverage mass economies of scale, access to mature software and device drivers, and a means of utilizing technology for various I/O functionalities. ASIC-based Bus Translation Bridges Balancing this need for an interconnect with a truly distributed architecture, that can be found in RapidIO, with the requirement to interface to server I/O peripherals, based on PCI, generally requires embedded system designers to implement ASIC-based translation bridges. In this case, it would involve an ASIC bridge that has a PCI endpoint and a Serial RapidIO endpoint, with the bridge translating the PCI protocol (PCI, PCI-X, or PCI-Express) to RapidIO. While providing essential functionality, these bridges have several performance drawbacks. Regardless of fine tuning adjustable parameters, bus translation bridges will inevitably force retries and disconnects. Combined with limited FIFO’s and inefficient pre-fetching, this will result in performance penalties in terms of latency and throughput that can negatively impact the greater system. Optimized Bridging Through Multi-Ported Memory Controllers Alternatively, bridges based around multi-ported memory controllers can overcome these performance penalties. Providing seamless, transparent access between endpoints with different topologies, such as PCI and Serial RapidIO, translation bridges based on multi-ported memory controllers do not suffer the disconnects and retries experienced with conventional bridges. These solutions require more total devices, including external memory, that result in occupying more board real estate and at a higher cost than alternative implementations. But for many applications, particularly those involving real time streaming data, this cost is easily offset by the overall system benefits. Based on a multi-ported memory controller, Micro Memory™ offers its CoSine™ FPGA on several current and forthcoming board-level form factors as an effective alternative to bridging between PCI-X and Serial RapidIO. In addition to optimized bridging capabilities, CoSine is a fully integrated System-on-Chip with FPGA processing resources for fixed-point DSP operations. For more information, visit www.micromemory.com/CoSine.html. by Mike Jadon, Director of Product Marketing, Micro Memory, LLC |