RapidIO Connections Newsletter - Summer 2005

Executive Director’s Perspective Transitions: RapidIO® technology forms the critical foundation for new and emerging applications in the midst of a world of change.
Design It Fault-Tolerant Systems and RapidIOŽ
Insights What are some of the benefits to having an open standard?
Member Connections • Debugging/Analyzing Serial Rapid IO High-Speed Serial Lanes by Chris Shelsky, Project Manager, Nexus Technology, Inc.

• RapidIO and Linux by Matt Porter of MontaVista Software, Inc.
RapidIO Product News New RapidIO-based solutions continue to debut in multiple market segments from silicon to board-level products.
The RapidIO Trade Association at Work Munich and Boston Developer Summits, Freescale Technology Forum, Supercomm
In the Spotlight The RapidIO Trade Association and standard continue to be sought after news in the industry.
Where to Network Visit with RapidIO Trade Association members, learn about products and see live demonstrations.
RapidIO Hall of Fame "Did You Know?" email campaign a success!
Changes Some parting thoughts from Dan Bouvier as he steps down from the RapidIO Steering Committee.
RapidIO Reflections: Significant interest in RapidIO technology from a wide cross section of customers

Member Connections:

Debugging/Analyzing Serial RapidIO High-Speed Serial Lanes by Chris Shelsky, Project Manager, Nexus Technology, Inc.

Serial RapidIO was developed to “address the need for a high-performance; low pin-count, and low-power serial packet-switched system level interconnect to be used in a variety of applications as an open standard.” The advantages of this new serial interconnect when compared to previous parallel architectures are many. However, traditional methods used for debug and analysis are no longer enough.

The ability to snoop and record the activity on a high-speed Serial RapidIO point-to-point lane(s) without disturbing the characteristics and behavior of the bus would provide a wealth of information for design engineers who strive to implement Serial RapidIO into their designs. This 8b/10b encoded link can have one or four differential (1.25, 2.5 or 3.125 Gbaud) lanes each carrying data and an embedded clock. These links have a “link protocol” that contains individual elements such as packets, control symbols and the serial bit encoding scheme. Debugging and analyzing this complicated architecture presents a formidable challenge.

Serial RapidIO was developed to “address the need for a high-performance; low pin-count, and low-power serial packet-switched system level interconnect to be used in a variety of applications as an open standard.” The advantages of this new serial interconnect when compared to previous parallel architectures are many. However, traditional methods used for debug and analysis are no longer enough.

Problems Associated with Traditional Methods of Debug

Parallel bus debug has historically been accomplished using a high-speed oscilloscope and a logic analyzer. An oscilloscope is used to validate the electrical characteristics of a bus such as overshoot, undershoot, jitter, noise, and skew. A logic analyzer is used to acquire, store and disassemble parallel data. Together an oscilloscope and a logic analyzer are a powerful solution for debug and analysis.

While an oscilloscope can still be used to accomplish the characterization of a Serial RapidIO bus, a logic analyzer is designed to acquire parallel data and cannot directly acquire serial encoded data with an embedded clock. Losing this ability leaves the engineer blind to the actual traffic on the bus. All that can be seen is the electrical integrity of the bus and data that is sent and received by agents on the bus. The actual point-to-point links cannot be monitored.

Gaining Visibility of the Serial Data Stream

Ideally, an interface box is needed to de-serialize the Serial RapidIO data into parallel words which can be presented to the logic analyzer for acquisition, saving and analysis. This provides the ability to snoop the Serial RapidIO bus and preserve the debug and analysis capability that designers have historically and successfully used on older parallel designs.

Probing the Serial RapidIO Bus – Where to Probe

A method of probing the bus is also required. While a single point of contact seems to be the best solution it also presents unique concerns. Since Tx or Rx signals are ideally probed at the source or destination on a point-to-point bus, choosing a central location on the bus does not provide the best signal for either Tx or Rx. An ideal solution would be to probe individual links at specific locations on a target where the signal is representative of what should be analyzed.

Optimal Debug with Pre-processor and Flexible Probing

Nexus Technology, in conjunction with Tektronix, has developed probing solutions and the interface necessary for flexible probing and monitoring of Serial RapidIO traffic using a Tektronix TLA Series logic analyzer. A condensed, connectorless probe can be used on targets with the appropriate footprint to probe up to two, 4x-links simultaneously. Alternatively, single-channel probes which can be soldered to an appropriate via or component pin are also available so that each lane can be probed individually without the need for probe footprints on the target. Using single-channel probes also provides the ability to monitor the source or destination point on the Serial RapidIO bus even if they are physically separated on the target.

Either of these probing solutions connects to a Serial RapidIO pre-processor box which performs all the functions necessary to parallelize up to two, 1x or 4x, Serial RapidIO links running at 1.25, 2.5 or 3.125 Gbaud. The parallel data is then sent to the logic analyzer through standard logic analyzer probes for acquisition and disassembly. Custom disassembly software is also provided so that 8b/10b codes, control symbols, packets and packet payloads are displayed. For more information please visit www.busboards.com/products/bus/srio or contact Nexus Technology, Inc. 877-595-8116.

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