RapidIO Connections Newsletter - Fall 2005In this issue...Design It:RapidIOŽ Technology for Wireless Infrastructure The wireless infrastructure is an excellent target for the use of RapidIO technology. The cellular wireless infrastructure network can be divided into three main parts the MSC/GSN, the radio network controller and basestation. Data and calls entering the system from the network arrive via a mobile switching center (MSC) from the public switched telephony network (PSTN) or via a general packet radio system (GPRS) support node (GSN) from the IP network. There are many functions performed on the data at the network interface, including protocol termination and translation, routing switching, and transcoding and transrating of telephony and video signals. Normally, the number of MSC and GSN nodes in a network is kept to a minimum, so that each node processes a large number of calls. Therefore, the data rates are large, on the order of 10-100 Gigabit/s (Gbps), and high-bandwidth switching and routing occurs. Transcoding and transrating large quantities of voice and video signals requires banks of DSP farms that are connected to the routers by high-speed interconnect. Once the data has been formatted for the wireless infrastructure, it passes to the radio network controller (RNC) in the radio access layer of the network. The RNC controls access to the basestations and is responsible for setting up and tearing down connections between users and the network. The RNC is responsible for managing the mobility of a user who is moving around between cells and networks. A certain amount of signal processing occurs in the RNC to allow processing of data from multiple basestations. The basestation is responsible for maintenance of the physical link to the user. Each basestation keeps in contact with the users who are physically located within its cell. A great deal of signal processing occurs in the basestation. Like the MSC and GSN nodes, a basestation will typically house racks of DSP - and ASIC-laden digital baseband boards. RF processing and power amplification also occurs in the basestation. All of the RF and digital baseband cards are connected to each other and to miscellaneous control and interface cards via high-speed backplane links. The chip-to-chip data rate on these boards is also quite high and rising as higher data rate technologies such as 3G are deployed. There are several standards in use today for wireless infrastructure. These include WCDMA, GSM, EDGE, IS95 and CDMA2000. The multitude of standards is due to competition between companies and national organizations as well as the evolution of standards to provide new features and higher data rates. The industry trend is toward higher data rates and more capacity in a single cell, leading directly to increased data rate requirements in the wireless infrastructure equipment itself. Mobile Switching Center/GPRS Support Node Core Network Interface Calls are constantly being set up and torn down; therefore the data flow in the system is very dynamic. Microprocessors are typically employed as control processors responsible for managing the flow of data. They will perform load balancing on the boards to ensure that the maximum number of calls can be handled, even with a rapidly changing traffic pattern. Therefore, there is a mixture of data and control information flowing to and from the boards. Voice calls are very latency-sensitive. Too much delay in the transmission of the voice signal and the quality of the phone call will suffer. Echo cancellation processing must also be performed to remove echoes from the conversation. This leads to very strict latency constraints in the MSC processing. Transcoding and Transrating The DSP farm that is used to process this data is a classic embedded processing application. In a typical board level architecture, the data enters and leaves the system in packets that are transmitted across a backplane. Each packet is sent to the controller (usually a microprocessor of some kind), which extracts the channel information so that the destination of the packet can be ascertained. The controller then directs the protocol and routing device to route the packet to the DSP that is responsible for processing that channel. The protocol termination and routing chip is usually an FPGA or ASIC designed specifically for the board. Network processors are now seeing some use in this application. The controller must also be able to receive and transmit control information to and from each DSP so that the state of the DSP is known and changes in the channel allocation of a DSP can be communicated. Clearly, there is a lot of routing of both control and data information through a system like this. In addition, because current systems lack a bus that is scalable to the backplane, the protocol on the backplane is often different from that on the board, forcing the board controller and protocol termination devices to bridge between different bus protocols between the board and the backplane. Radio Network Control The resource management function of the RNC refers to the RNC responsibility for keeping track of the available radio spectrum network capacity, and determining which of the available spectra should be used for any given call. There is a high basestation to RNC ratio, ranging from 100 to 1000 to 1. Consequently, data rates at the RNC are quite high; they are about the same order as at MSC level. The need for high-speed interconnects at the chip, board and subsystem level have grown quite acute. Basestation The controller card decodes the basestation-specific control messages and sets up the baseband modem cards to correctly transmit and receive user data. There may be several baseband modem cards and several analog/RF cards in a single rack. The baseband modem card is sometimes split into transmit and receive cards, which have communication requirements owing to closed power control loops. The data rate requirement for the network-to-baseband modem cards is in the tens of Mbps. The data rate requirement for the baseband -to-analog interface is several Gbps. Both interfaces require a mixture of control and data. Basestations come in a variety of sizes, from picostations that serve a single building to large macro cells that can cover hundreds of square kilometers in rural settings. The number of voice users supported by a single basestation varies from tens to thousands. Different basestation rack configurations have been developed to cope with this variety, but since they share many components a flexible, scalable interconnect is required. The baseband modem card itself presents additional interconnect challenges. A typical third-generation WCDMA modem card architecture with the on-chip interconnect, poses several challenges:
Simplification with RapidIO Interconnect Technology In the basestation, a variety of protocols are currently used to connect several boards together. The baseband modem board makes use of a variety of mostly proprietary interconnects, some of which require significant bandwidth and low latency. Both control and data information are transmitted through the system. A single protocol that can be used for both the control and data information and for both backplane and chip-to-chip communication minimizes chip count, simplifies the development of different-sized basestations, reduce development cost and can also reduce time to market. The data rate requirements for basestations continue to increase as the move to third generation (3G) wireless standards brings higher user data rates. The number of antennas supported in a single basestation is also increasing, owing to increased use of techniques such as sectorization and adaptive antenna array processing. A protocol that can support a variety of data rates can be instrumental in reducing the cost and power of the baseband card. Though the analog card to baseband card interface could be supported by RapidIO, recent moves to standardize this interface in OBSAI and CPR have focused on frame-based, rather than packet-based protocols. This is because the data transfer is regular and very low jitter is desired. The data is being generated by analog-to-digital converters (ADCs) or is being sent to digital-to-analog converters (DACs). Lower jitter leads to less buffering on the analog card. But there is no reason that streaming write transactions with relatively small packets could not be used in RapidIO to achieve a similar effect. Independent studies at Texas Instruments and Ericsson have shown that the physical area of a RapidIO port that is constrained to a streaming write is about the same as that of an OBSAI or CPRI port. With RapidIO, this interface would allow the use of standard RapidIO switches and routers, leading to less expensive, more flexible solutions. However, as at this point the industry push is to converge on a frame-based protocol, RapidIO switches with OBSAI and CPRI bridges may well be required to serve this market. Excerpted from RapidIO: The Embedded System Interconnect by Sam Fuller, John Wiley & Sons, Ltd., 2005, Chapter 13, by Alan Gatherer and Peter Olanders. |