Design Tips

Supporting PMCs/XMCs in a RapidIO Multicomputer

By Eran Cohen Strod, Director, Product Marketing, Defense Electronics Group
Mercury Computer Systems, Inc.

Mezzanine cards have evolved as an effective way to implement flexible system designs, supporting ever-changing user requirements for I/O and adjunct processing. For high-performance embedded systems, the PCI Mezzanine Card (PMC) has become the most broadly accepted standard. Although their I/O bandwidth is limited by the speed of the PCI bus, PMC modules are still important to RapidIO system designers because they support such a wide array of I/O device interfaces.

The XMC standard (VITA 42) was developed as a superset of the PMC standard. It provides the same level of mezzanine flexibility as the PMC, with the added advantage of a high-bandwidth, switch fabric interface. VITA 42 is flexible enough to support the various switch fabric standards under the umbrella of a single standard; it is divided into a base standard and derivative protocol standards, or dot specifications. Each derivative protocol standard maps a specific switch fabric protocol onto the VITA 42 base, including VITA 42.1 for Parallel RapidIO and VITA 42.2 for Serial RapidIO.

A PMC is actually defined by a combination of two IEEE standards that were finally accepted in 2001. (Of course vendors began creating PMC cards based on the proposed version of these specs long before they were officially accepted.) IEEE 1386 defines the Common Mezzanine Card (CMC). The physical and mechanical specification of the PMC.IEEE 1386.1 is the electrical standard for a PMC, mapping the PCI bus signals onto the CMC connectors. The PMC interface standard consists of four board-to-board 1.00 mm dual-row 64-pin connectors, labeled P1 thru P4. A 32-bit PCI bus uses the P1 and P2 connectors, while a 64-bit PCI bus uses P1, P2, and P3. In either mode, P4 is available for user-defined signaling.

The VITA-42 XMC standard extends the PCI interface by the addition of two new high-speed connectors to the four PMC connectors. These two new connectors, designated P5 and P6, provide XMC RapidIO connections that are independent from the PCI bus support for the P1-P4 connectors. These additional connectors include power and ground pins, so VITA 42 provides the option of designing a XMC that only includes the two RapidIO connectors. While any type of module can be designed with a PMC and/or XMC site, overall system architecture often leads to a carrier board created specifically for that purpose.

Since VITA 42 was designed for backwards compatibility, a carrier board with mezzanine sites designed to the VITA 42 specification can support both PCI and RapidIO mezzanine connections, even if the particular mezzanine card selected supports only one or the other. This allows system designers a high level of flexibility to deal with a range of I/O bandwidths.

The carrier board must also provide the interface from the PMC/XMC to the RapidIO fabric. For a PMC, this takes the form of a PCI-to-RapidIO bridge. For an XMC, a bridge chip is not required. Instead, the carrier board needs to connect the fabric XMC pins to a local RapidIO switch, or to a system level switch card via backplane connections.

The bridging from PCI to RapidIO is well defined in the RapidIO System and Device Interoperability Specification. PCI is a load/store transaction architecture which easily maps to RapidIO IO logical layer transactions. Once a system is initialized, neither the RapidIO fabric nor the PCI IO devices need to be aware that any bridging is taking place. This same model will hold through when the industry eventually produces PCI Express mezzanine modules as PCI Express transactions conform to the same PCI architecture. The advent of PCI Express as a future IO interconnect will somewhat simplify bridging implementations because implementations of RapidIO and PCI Express can share the same SerDes block, although PCI Express runs slower per lane that RapidIO.

The mezzanine carrier board usually includes a general purpose processor which controls data movement between the PMC/XMC and the rest of the RapidIO system. In most applications, this processor runs a common operating system such as VxWorks, or Linux, so that standard COTS drivers can be used to control the PMC/XMC.

To support a user application, the PMC/XMC module needs to exchange information with the rest of the RapidIO system, describing the data transfers pertaining to the PMC/XMC and including destination addresses and target identifiers for each transfer. This is typically handled by a portion of the application code that acts as a proxy between the endpoint on the PMC/XMC card and the rest of the multi=computer system, assuming responsibility for the exchange of information.

For PMC/XMC modules, the local processor on the carrier board usually acts as the proxy and handles the information exchange. Writing this proxy software for a multi=computer system can be a challenge. In a Mercury system, a set of well defined application programming interfaces (APIs) facilitate the extraction of the proper information in a standard fashion. This allows most XMC or PMC devices to connect to sophisticated, high performance, data movement middleware libraries, such as the Mercury PAS (Parallel Acceleration System) library with minimal effort. Such a software interface provides maximum flexibility, supporting both PMCs and XMCs and managing data streams with a range of different characteristics. For more information, visit Mercury Computer Systems at http://www.mc.com.