Design Tips

Plan Ahead for Serial RapidIO Validation

By Barbara Aichinger, Vice President, FuturePlus Systems

Serial-interface designers are facing higher speeds and denser designs. With these challenges come the complexity of design validation and test. Serial RapidIO designers need to look no further than their favorite logic analyzer vendor for a solution to these problems. Engineers have relied for decades on logic analyzers as an integral part of their validation and debug strategy. Today is no different. For the tried and true logic analyzer to interface to the new multi-gigabit (Gbps) architectures analysis probes are essential. Analysis probes translate high-speed serial interfaces into signals that can be understood by the traditional logic analyzer. Such products come complete with software that runs on the logic analyzer to give the user a complete decode of the bus traffic. There is no need to look at cryptic hex or binary characters. Analysis can be done from a high level graphical view or from a detailed text view (see Figure 1).

Fig.1 PhotoFig. 2 Photo

Figure 1. Detailed text and high level graphical
view of Serial RapidIO data. (Photos courtesy of FuturePlus Systems)

How to Connect Photo

Figure 2: Connectorless footprint and compression probe. (Photo courtesy of Agilent Technologies)

How to connect
Up front planning is required to connect the Analysis probe to the Serial RapidIO target. Connectorless probing was adopted in order to non-intrusively probe 1.25 Gbps to 3.125 Gbps speeds. The footprints, or pads that are incorporated onto the PCB are standardized so that multiple vendors' test equipment can attach to them. This is a win for the industry, since engineers can design in one footprint at design time, and then pick the test equipment vendor when they are ready to test. In the past the footprints were different between the vendors, so the design engineer had to make a commitment to a test vendor during design time. If that vendor delivered late or ended up not having the best equipment, the project team was in trouble.

For Serial RapidIO the industry is using the same connectorless footprint that was used for the PCI Express industry. This allows design reuse and opens up the test equipment field to new players. This new style of connectorless probing includes a compression interconnect from the analysis probe to the target. The fact that there is no connector lowers the electrical loading of the analysis probe on the target. This leads to higher signal fidelity for the analysis probe and less electrical loading on the target. Figure 2 shows an example of a connectorless footprint and a compression probe.

Since Serial RapidIO is a single lane or a four-lane, bidirectional link, all signals can fit on what is commonly referred to as the half sized footprint. Complete details concerning the size of the footprint and pinout for Serial RapidIO can be found on the FuturePlus Systems web site at: http://www.futureplus.com/download/appnotes/an_srio_fs4410.pdf

Footprint Photo

Figure 3: Flying lead set for high performance probing. (Photo courtesy of Agilent Technologies)

No room for a footprint?
Even though the Serial RapidIO footprint is small there may not be enough room on some smaller and more densely packed designs for this footprint. Due to this constraint vendors have made a flying lead set available that is small and flexible. Figure 3 shows this flying lead set. Designing Gbps links into today’s products need not compromise testing. Information and tools are available to help design engineers tackle the most difficult test scenarios. Planning ahead for validation and debug is the key to successful product introduction.

About the Author:
Barbara P. Aichinger is Vice President of FuturePlus Systems, the leading worldwide analysis probe provider. She has over 20 years experience with various bus architectures and has spoken on Test and Measurement topics world wide. Barbara can be reached at Barb.Aichinger@futureplus.com. FuturePlus Systems product line can be seen at www.futureplus.com.

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