Industry Insights

Interworking: Solidifying The Complementary Roles Of PCI Express, RapidIO and Ethernet In Next-Generation Systems

by Ann Thryft, Senior Editor, RTC Magazine and COTS Journal

The interconnect landscape looks pretty crowded right now, with several I/O standards emerging that appear to compete for chip-to-chip and board-to-board interfaces. The three main interconnect choices are Ethernet, PCI Express (PCIe) and RapidIO. Although these share certain similarities and compete in some areas, each is finding a place in the larger landscape of system architecture.

Many switched fabrics, such as PCIe and the serial version of RapidIO, Serial RapidIO, share common electrical and signaling characteristics, making it easy for designers and integrators to mix fabric-specific solutions based on off-the-shelf silicon with fabric-agnostic products that use FPGAs. Although most switched fabric interconnects share a common physical layer, their capabilities and the topologies they support differ considerably.

Since this is the era of everything-over-IP, and therefore everything-over-Ethernet, Ethernet and its variations will continue to be deployed in a widening range of uses, especially for network connectivity and IP-based data traffic. Switched Gigabit Ethernet is becoming the preferred interconnect for high-speed, high-bandwidth IP networks connecting subsystems and chassis.

Subsystem- and board-level products are, of course, dependent on their chip eco-systems. While Ethernet functionality has been included in systems and chips for some time, PCIe and RapidIO are rapidly joining it. PCIe is now found widely as an emerging standard for board-to-peripheral interconnects. In addition, PCIe is being included as a native processor interface on embedded CPUs and is appearing on an increasing number of merchant communications chips. The result is a rise in its use for chip-chip interconnections.

RapidIO is being used to interconnect DSPs and PowerPCs, especially in telecom. This is only logical, since the standard was originally developed for communications and networking applications, as well as signal processing. Serial RapidIO interfaces will appear on more CPUs this year.

Serial RapidIO, like the Advanced Switching Interconnect (ASI) evolution of PCIe, was initially designed as a peer-to-peer fabric, and both support several topologies beyond the hierarchical tree structure of PCIe. Both Serial RapidIO and ASI will probably be used to provide chassis-wide and multi-chassis switched fabrics that interconnect system nodes. In particular, Serial RapidIO will likely be found performing data movement in high-performance, next-generation military signal processing systems because of its more efficient packet structure, flexible network topologies and higher bandwidth (10 Gbytes/s total).