Technical Insights
The 10G Serial Buffer:
Bringing Advanced Memory Solutions to the RapidIO Ecosystem
By Michael Olsen, Integrated Device Technology
www.IDT.com
Problem: Increasing the Ability to Buffer Serial Packets in High-Bandwidth RapidIO Systems
Typically, high-throughput environments — such as wireless base stations and other digital signal processor (DSP)-intensive applications — consume large amounts of system resources, including high-density memory.
For example, today's wireless base stations need to see the same set of data multiple times to decode different sets of information. Specifically, in 3G systems the same hardware module (DSP or chip rate processing ASIC) needs to access 10ms of sample frame data to do random access channel (RACH) decoding first, and data channel (DCH) second, with this same data being accessed by all of the DSPs in the cluster. This sample-compare memory problem generally requires the consumption of costly system resources to achieve the requisite speed and limits the capacity of the base station system to support value-added services at a competitive price point.
One approach is to break the large samples into fragments for nested calculation, but this consumes extra processing cycles and reduces overall throughput. Another is to dramatically enlarge one local memory on a board for use as a buffer that feeds the other local memories. This complicates memory management and only serves as a band-aid that mitigates the bottleneck problem somewhat, but does not solve it. And yet a third approach is to store the data in FPGA/DSP combinations — a custom design with high design cost/risk. Clearly, a new approach is mission-critical to the success of providing cost-effective, high-performance systems.
The Solution: Bringing a 10G Serial Buffer into the RapidIO Ecosystem
Enabling true 10 Gbps data transfer rates for DSP-intensive applications, with comparatively low I/O count and BOM, the 10G serial buffer is the first and only Serial RapidIO-based memory available today. Depending upon the specific alternative approach used for comparison, the 10G serial buffer can:
- Dramatically improve performance by eliminating local memory bottlenecks, or
- Reduce silicon area by eliminating or reducing the need for local memory entirely, or
- Significantly simplify design by eliminating complex memory management schemes
Able to connect to any serial RapidIO switch or end-point, the 10G serial buffer has 18 Mbits of internal memory, plus connection to 72 Mbits of external QDR SRAM - another industry first. This sum total of 90 Mbits enables a DSP to compare consecutive data samples in one calculation, thus eliminating the time-consuming nested calculations required by capacity-limited local memories.
Moreover, the 10G serial buffer contains intelligent monitoring and control circuitry that automatically identifies and compensates for dropped data packets to maintain data synchronicity — a vital function for high-performance systems. This product can also operate as a master, recognizing when and where data must be sent, and initiating data transfers with no additional assistance from the DSPs or other RapidIO end-points in the system.
Note that while the example above described a base station application, the 10G Serial Buffer will also meet the needs of other applications requiring large buffers. For instance: medical imaging (CAT scans, MRIs — anywhere that larger files are being transferred), high-speed communications applications (large lines that need to be buffered), and any DSP-cluster applications (such as radar, data-acquisition and sampling).
