Technical Insights

A Look To The Future: RapidIO Technical Working Group

By Travis Scheckel, Texas Instruments and Chair of the RapidIO Technical Working Group

As Chair of the Technical Working Group, I'm excited to give you a preview of the soon to be released Rev 2.0 specification. The unique mix of RapidIO TWG members, including system OEMs, silicon and software providers, have invested a great deal of insight, time, and energy into the creation of this specification in order to build on RapidIO standard's current success and take it to the next level in interconnect technology. While maintaining backward compatibility, the new Rev 2.0 specification features significant enhancements concentrated in two major areas: a higher performance serial physical layer and a versatile, higher utilization data plane.

Performance has always been a cornerstone of RapidIO, and Rev 2.0 certainly delivers with abundance. In addition to wider port configuration options, we have introduced higher signaling rates up to 6.25Gbps per lane. The electrical signaling specifications are based on OIF compatible SerDes for optimal technology re-use. With these options, RapidIO is an outstanding choice for virtually all embedded system interconnect solutions, offering scalable bidirectional bandwidth from 2 Gbps to 160 Gbps. The new Rev 2.0 serial physical layer features include:

  • Link width options are 1x, 2x, 4x, 8x and 16x
  • Data rates of 1.25, 2.5, 3.125, 5.0 and 6.25 Gbaud
  • Electrical specifications compatible with XAUI and OIF SerDes
  • Support for virtual channels with independently managed buffer resources
  • Scrambled and 8b/10b encoded data
  • Support for DFE based receivers for greater channel options
  • Supports StatEye channel compliance testing
  • Auto detection mechanisms for system and link configuration

The new data plane enhancements offer carrier grade functionality and fabric performance. This is accomplished utilizing concepts such as class of service (COS) and Virtual Output Queuing (VoQ) to have finer control on packets, as well as, taking advantage of the newly defined physical layer VCs to achieve higher fabric utilization and guaranteed levels of performance among endpoint applications. RapidIO has introduced a new packet type and employed various levels of flow control and supported traffic management techniques. The new data streaming format supports large PDU sizes, selectable MTU size, COS field designator, multicast operations, and can optionally support VC applications with allowable data loss. Added data plane support includes:

  • Thousands of endpoint data streams with concurrent PDUs up to 64KB
  • COS support with hundreds of traffic classes
  • Encapsulation of any arbitrary protocol
  • Endpoint arbitration of PDU Segmentation and Reassembly (SAR) contexts
  • Endpoint management to throttle traffic flows between class/stream based queues
  • VoQ support to greatly reduce head-of-line (HOL) blocking

With these enhancements, the RapidIO specification stands out as the interconnect that meets the needs of next generation communication and embedded systems.

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