RapidIOŽ Connections - Q4 2007
Association News
The RapidIO Trade Association: Delivering the
Information Designers Need to Make
Informed Choices
By Tom Cox, Executive Director, RapidIO Trade Association
Quality of service (QoS) is an inherent part of the RapidIO specification,
implemented directly in hardware and enabling traffic to be classified into as
many as six prioritized logical flows. While the mechanism for forward progress
in the fabric relies upon ordering rules at the physical layer to give responses
higher priority, the degree to which prioritization results in lower average
latency or jitter for a particular flow is specific to the actual implementation.
For example, more aggressive switches might make ordering decisions based upon a
flow's priority, source, and destination ID fields while less aggressive designs
might only utilize the priority field.
QoS is also affected by specific fabric arbitration policies. While the
specification explicitly defines prioritized flows, developers are free to choose
the particular arbitration policies to put into place to prevent starvation of
lower-priority flows, such as the well-known leaky-bucket scheme. As even the
least aggressive design must support these mechanisms, higher-priority flows are
guaranteed to demonstrate better lower-average latency.
For applications requiring even more aggressive and effective QoS, advanced flow
control and data plane capabilities are available. The RapidIO protocol defines
multiple flow control mechanisms at the physical and logical layers. By managing
physical layer flow control at the link layer, short-term congestion events are
effectively managed for serial and parallel applications using both receiver- and
transmitter-controlled flow control. Longer-term congestion is controlled at the
logical layer using XOFF and XON messages which enable the receiver to stop the
flow of packets when congestion is detected along a particular flow.
Receiver-only flow control, where the transmitter does not know the state of
receiver buffers and the receiver alone determines whether packets are accepted
or rejected based on receiver buffer availability, results in packets being
resent, creating wasted link bandwidth. Additionally, ordering rules require a
switch to send higher-priority packets before resending any packets associated
with a retry, aggravating worst-case latency for lower priority packets.
Transmitter-based flow control avoids bandwidth wasting retries by enabling the
transmitter to decide whether to transmit a packet based on receiver buffer
status. Through receiver buffer status messages sent to the transmitter using
normal control symbols, the transmitter is able to limit transmissions within the
maximum number of buffers available at the receiver. In general, priority
watermarks at the various buffer levels are used to determine when the
transmitter can transfer packets with a given priority.
A third link-level mechanism is available within the parallel PHY specification
which enables the receiver to throttle the packet transmission rate by requesting
that the transmitter insert a selectable number of idle control symbols before
resuming transmission of packets.
Revision 1.3 of the RapidIO specification achieves further efficiency and higher
throughput through the introduction of data plane extensions. Since data plane
fabrics can carry multiple data protocols, these extensions enable the
encapsulation of virtually any protocol using a data streaming transaction type
with a payload up to 64 Kbytes. Hardware-based SAR support is expected for most
implementations, with up to 256 classes of service and 64 K streams.
The upcoming 2.0 revision of the specification builds on revision 1.3
capabilities, introducing a new 5.0 Gbaud and 6.25 Gbaud PHY, lane widths up to
16x, 8 virtual channels with either reliable or best-effort delivery policies,
enhanced link-layer flow control, and end-to-end traffic management with up to 16
million unique virtual streams between any two endpoints.
The RapidIO protocol is a simple and efficient interconnect designed specifically
for high-speed embedded applications and appropriate to serve as a system-level
fabric. By implementing protocol processing in hardware, many quality of service
and flow control mechanisms are an inherent part of the PHY, maximizing
efficiency and throughput while minimizing latency and switch complexity. Backed
by new data plane extensions which enable RapidIO switches to encapsulate
virtually any data protocol, the RapidIO specification is an ideal interconnect
technology, enabling developers to consolidate interconnect layers, as well as
both control and data planes, into a single fabric, reducing cost while
increasing overall system reliability. Please click here for more information.
