RapidIO Specifications

Below is the public listing of RapidIO specifications and other design documents. Not all items are available for public viewing.

RapidIO Specification 2.0 has been approved and Released to the Public. 

Note: The current version of the specification has been updated per any outstanding errata. On going revisions are possible and may be in review.



RapidIO Document Description Access Date
RapidIO Specification
2.0
Defines extensions to the RapidIO specification includes errata
Part 1 to 12, Annex 1 & 2.
ZIP
03/2008
RapidIO Specification 1.3

Part 1: I/O System Logical Layer
Defines a rich variety of transaction types, such as DMA-style read and writes, that allow efficient I/O systems to be built. ANSI INCITS 413-2007
ISO/IEC 18372-2004 version 1

PDF 06/2005
RapidIO Specification 1.3

Part 2: Message Passing Logical Layer
Defines the message passing or software-based coherency functions that enable support for distributed I/O and processing requirements. PDF 06/2005
RapidIO Specification 1.3

Part 3: Common Transport
Specifies the header information added to a RapidIO logical packet and the way the header information is interpreted by a switching fabric. The RapidIO standard defines this mechanism independent of a physical implementation. PDF 06/2005
RapidIO Specification 1.3

Part 4: Parallel Physical Layer
Defines an 8-bit and 16-bit parallel (8/16 LP-LVDS), point-to-point interface. PDF 06/2005
RapidIO Specification 1.3

Part 5: Global Shared Logical Layer
Describes the standard approach for providing directory based coherent memory in a RapidIO-based multiprocessor system. Note: support for this feature is optional in RapidIO devices. PDF 06/2005
RapidIO Specification 1.3

Part 6: Serial Physical Layer Specification
Includes physical layer header, 8B/10B coding, symbol generation, buffer management, lane striping and driver and receiver characteristics. PDF 06/2005
RapidIO Specification 1.3

Part 7: Interoperability Specification
Defines interoperability requirements for RapidIO devices and also for RapidIO to PCI devices. PDF 06/2005
RapidIO Specification 1.3

Part 8: Error Management Extensions
Describes the optional error management extensions, including additional register definitions for collecting device state. Also describes standard maintenance transactions for reporting error conditions to host devices. PDF 06/2005
RapidIO Specification 1.3

Part 9: Flow Control Extensions
Describes optional extensions that provide XON/XOFF support to provide traffic management capabilities to manage congestion in more complex systems. PDF 06/2005
RapidIO Specification 1.3

Part 10: Data Streaming Logical Layer, Phase I
Defines a method for protocol independent encapsulation of payloads up to 64K bytes.
PDF 06/2005
RapidIO Specification 1.3

Part 11: Multicast Extensions
Defines a method for switch-based multicast of packets in a RapidIO network. PDF 06/2005
RapidIO Specification 1.3

Annex 1: Software/System Bring Up Specification
Builds on the Interoperability Specification to define a standard set of software API functions for use in system bring up. PDF 06/2005
RapidIO Specification 1.2 Access the archived 1.2 version of the specification, including the Errata document. Archive  
Hardware Interoperability Platform Document Describes the electrical and mechanical requirements for a RapidIO interoperability platform that supports both Serial and Parallel RapidIO links. Members Only 11/2002
Interoperability Checklists Rev 1.3 Device compliance checklists adhering to RapidIO Specification Revision 1.3. Members Only 09/2005
Bus Functional Model (BFM) Provides interoperability and compliance checking. It is supplied as a C model with Verilog wrapper. RapidIO Trade Association members have access to the BFM under a licensing agreement. Members Only